These get allocated and freed millions of times on this kernel tree.
Use a dedicated kmem_cache pool and avoid costly dynamic memory allocations.
Signed-off-by: Park Ju Hyung <qkrwngud825@gmail.com>
These get allocated and freed millions of times on this kernel tree.
Use a dedicated kmem_cache pool and avoid costly dynamic memory allocations.
Signed-off-by: Park Ju Hyung <qkrwngud825@gmail.com>
[@0ctobot: Adapted for 4.19]
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
There isn't a need for cpus_affine to be atomic, and reading/writing to
it outside of the global pm_qos lock is racy anyway. As such, we can
simply turn it into a primitive integer type.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Clearing dim layers indiscriminately for each blend stage on each commit
wastes a lot of CPU time since the clearing process is heavy on register
accesses. We can optimize this by only clearing dim layers when they're
actually set, and only clearing them on a per-stage basis at that. This
reduces display commit latency considerably.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Reading and clearing any errors from the VBIF error registers takes a
significant amount of time during kickoff, and is only used to produce
debug logs when errors are detected. Since we're not debugging hardware
issues in MDSS, remove the VBIF error clearing entirely to reduce
display rendering latency.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Explicit write memory barriers are unneeded here since releasing a lock
already implies a full memory barrier.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
The IRQ status reads are decoupled from the IRQ dispatcher, even though
the dispatcher is the only one using the IRQ statuses. This results in a
lot of redundant work being done as the IRQ status reader also reads the
IRQ-enable register and clears the IRQ mask, both of which are already
handled by the IRQ dispatcher. We can cut out the redundant work done in
the hardware IRQ handler by consolidating the IRQ status reads into the
IRQ dispatcher.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
These heavy checks for seeing if autorefresh is enabled are unneeded
when the autorefresh config is disabled. These checks are performed on
every display commit and show up as using a significant amount of CPU
time in perf top. Skip them when it's unnecessary in order to improve
display rendering performance.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Every atomic frame commit allocates memory dynamically to check the
states of the CRTCs, when those allocations can just be stored on the
stack instead. Eliminate these dynamic memory allocations in the frame
commit path to improve performance. They don't need need to be zeroed
out either.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Diab Neiroukh <lazerl0rd@thezest.dev>
Remote register I/O amounts to a measurably significant portion of CPU
time due to how frequently this function is used. Cache the value of
each register on-demand and use this value in future invocations to
mitigate the expensive I/O.
Co-authored-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
[@0ctobot: Adapted for msm-4.19]
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
The plane states allocation and free show up on perf top as taking up a
non-trivial amount of time on every commit. Since the allocation is
small, just place it on the stack to eliminate the dynamic allocation
overhead completely.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Diab Neiroukh <lazerl0rd@thezest.dev>
More often than not, get_vsync_info() is used to only get the write line
count, while the other values it returns are left unused. This is not
optimal since it is done on every display commit. We can eliminate the
superfluous register reads by adding a parameter specifying if only the
write line count is requested.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Diab Neiroukh <lazerl0rd@thezest.dev>
The cleanup portion of non-blocking commits can be offloaded to little
CPUs to reduce latency in the display commit path, since it takes up a
non-trivial amount of CPU time. This reduces display commit latency.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
[lazerl0rd: Adjust for Linux 4.19, with different commit cleanup.]
Signed-off-by: Diab Neiroukh <lazerl0rd@thezest.dev>
Since we know an interrupt will be arriving soon when a frame is
committed, we can anticipate it and prevent the CPU servicing that
interrupt from entering deep idle states. This reduces display rendering
latency.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Diab Neiroukh <lazerl0rd@thezest.dev>
This unused debug print wastes CPU time when writing to registers,
resulting in perf top reporting a decent chunk of time spent inside
sde_reg_write(). Removing the debug print gets sde_reg_write() off perf
top's radar.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
A measurably significant amount of CPU time is spent in these routines
while the camera is open. These are also responsible for a grotesque
amount of dmesg spam, so let's nuke them.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Instead of registering a custom IRQ notifier, we should just use the PM
QoS framework's PM_QOS_REQ_AFFINE_IRQ feature.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
These are blocking some CPUs in the LITTLE cluster from entering deep
idle because the driver assumes that display rendering work occurs on a
hardcoded set of CPUs, which is false. We already have the IRQ PM QoS
machinery, so this cruft is unneeded.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
cpumask_set_cpu() uses the set_bit() helper, which, in typical kernels
prior to 4.19, uses a spin lock to guarantee atomicity. This is
expensive and unneeded, especially since the qos functions are hot code
paths. The rest of the cpumask functions use the bitmap API, which is
also more expensive than just doing some simple operations on a word.
Since we're operating with a CPU count that can fit within a word,
replace the expensive cpumask operations with raw bitwise operations
wherever possible to make the pm_qos framework more efficient.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
These kthreads (particularly crtc_event and crtc_commit) play a major
role in rendering frames to the display, so affine them to the prime CPU
cluster, matching the DRM IRQ.
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Currently, during ctl reset in video mode, irq register or
unregister might result in race condition with vblank
enable/disable calls on event thread resulting in enable
cnt mismatch. This change adds mutex locks to avoid race
conditions in such cases.
Change-Id: I45aef19864475ac1b02dd8e84810eee233fc60ea
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
In pstate_cmp the plane_state structures are accessed
without checking it is allocated or not, which leads to
null pointer dereference. To fix it NULL check is added.
Change-Id: I5982138b396b70979205d87bc9aa260d9501fee0
Signed-off-by: Mahadevan <mahap@codeaurora.org>
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
Add changes to fix the null dereference in
drm_atomic_get_property caused by connector->state
being NULL. This change allows the drm_mode_config_reset
operation to happen before drm_dev_register to avoid this.
In current scenario, connector->state->crtc is being
accessed due to call to drm_mode_getconnector ioctl with
the drm_mode_config_reset operation pending.
Change-Id: I374d9485819fad85100d1837f4ae22fc2a3ccc40
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
Fix out of bound access that occurs when reading dsi
commands with custom non 4 bytes aligned payload.
When misaligned, the code is overfetching data due
to 32 bits reading constraint. This creates an offset
in receiving buffer. Using a local copy buffer large
enough to hold the extra bytes fixes the issue.
Bug: 139655049
Change-Id: Ia0ee791d2e87639edd58191cfd5cb6f8f825f8c8
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
(cherry picked from 8f44ae7ca74a5faf6d7caaac48899192301f250d)
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
Move the hist irq handling out of callback function, i.e., the hw
interrupt irq_lock context, to avoid dead lock between crtc spin_lock
and irq_lock. This change also extends crtc spin_lock coverage in
_sde_cp_crtc_enable_hist_irq to prevent null pointer dereference on
event node, which can be deleted during crtc event de-registration.
Change-Id: Iadaed54ab93c4c4abe065a8762d2addccb0c65c6
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
This driver provides exposure adjustment function by Qcom SDE dim
layer without change panel hardware brightness to avoid PWM flicker
on OLED devices. Thanks to OnePlus' opensource code for inspiring
me to use dim layer.
Use expo_calc_backlight to remap brightness with hardware and SDE,
checking Disable Hardware Overlays in developer options if you face
blocks with differents brightness issue.
[Ayrton: Backported from lahaina to SMxx50.0 SDE Driver for compatibility]
Signed-off-by: DevriesL <therkduan@gmail.com>
Signed-off-by: Carlos Ayrton Lopez Arroyo <15030201@itcelaya.edu.mx>
Add a sysfs mechanism to track the idle state of display subsystem.
This allows user space to poll on the idle state node to detect when
display goes idle for longer than the time set.
Bug: 139655049
Bug: 126304228
Change-Id: I21e3c7b0830a9695db9f65526c111ce5153d1764
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Robb Glasser <rglasser@google.com>
(cherry picked from commit 11a2193b434cb3130743fbff89a161062883132e)
Signed-off-by: Ken Huang <kenbshuang@google.com>
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
