e24c2d963a
After seeing, at best, "guesses" as to the following kind of information in several drivers, I decided that we really need a way for platforms to specifically give advice in this area for what works best with their PCI controller implementation. Basically, this new interface gives DMA bursting advice on PCI. There are three forms of the advice: 1) Burst as much as possible, it is not necessary to end bursts on some particular boundary for best performance. 2) Burst on some byte count multiple. A DMA burst to some multiple of number of bytes may be done, but it is important to end the burst on an exact multiple for best performance. The best example of this I am aware of are the PPC64 PCI controllers, where if you end a burst mid-cacheline then chip has to refetch the data and the IOMMU translations which hurts performance a lot. 3) Burst on a single byte count multiple. Bursts shall end exactly on the next multiple boundary for best performance. Sparc64 and Alpha's PCI controllers operate this way. They disconnect any device which tries to burst across a cacheline boundary. Actually, newer sparc64 PCI controllers do not have this behavior. That is why the "pdev" is passed into the interface, so I can add code later to check which PCI controller the system is using and give advice accordingly. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
172 lines
6.0 KiB
C
172 lines
6.0 KiB
C
#ifndef __SPARC_PCI_H
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#define __SPARC_PCI_H
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#ifdef __KERNEL__
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/* Can be used to override the logic in pci_scan_bus for skipping
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* already-configured bus numbers - to be used for buggy BIOSes
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* or architectures with incomplete PCI setup by the loader.
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*/
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#define pcibios_assign_all_busses() 0
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#define pcibios_scan_all_fns(a, b) 0
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#define PCIBIOS_MIN_IO 0UL
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#define PCIBIOS_MIN_MEM 0UL
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#define PCI_IRQ_NONE 0xffffffff
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extern inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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extern inline void pcibios_penalize_isa_irq(int irq)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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/* Dynamic DMA mapping stuff.
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#include <asm/scatterlist.h>
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struct pci_dev;
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/* Allocate and map kernel buffer using consistent mode DMA for a device.
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* hwdev should be valid struct pci_dev pointer for PCI devices.
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*/
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extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
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/* Free and unmap a consistent DMA buffer.
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* cpu_addr is what was returned from pci_alloc_consistent,
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* size must be the same as what as passed into pci_alloc_consistent,
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* and likewise dma_addr must be the same as what *dma_addrp was set to.
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*
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* References to the memory and mappings assosciated with cpu_addr/dma_addr
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* past this call are illegal.
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*/
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extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
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/* Map a single buffer of the indicated size for DMA in streaming mode.
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* The 32-bit bus address to use is returned.
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*
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* Once the device is given the dma address, the device owns this memory
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* until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
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*/
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extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
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/* Unmap a single streaming mode DMA translation. The dma_addr and size
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* must match what was provided for in a previous pci_map_single call. All
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* other usages are undefined.
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*
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* After this call, reads by the cpu to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/*
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* Same as above, only with pages instead of mapped addresses.
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*/
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extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
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unsigned long offset, size_t size, int direction);
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extern void pci_unmap_page(struct pci_dev *hwdev,
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dma_addr_t dma_address, size_t size, int direction);
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scather-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
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/* Unmap a set of streaming mode DMA translations.
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* Again, cpu read rules concerning calls here are the same as for
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* pci_unmap_single() above.
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*/
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extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
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/* Make physical memory consistent for a single
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* streaming mode DMA translation after a transfer.
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*
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* If you perform a pci_map_single() but wish to interrogate the
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* buffer using the cpu, yet do not wish to teardown the PCI dma
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* mapping, you must call this function before doing so. At the
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* next point you give the PCI dma address back to the card, you
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* must first perform a pci_dma_sync_for_device, and then the device
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* again owns the buffer.
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*/
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extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
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/* Make physical memory consistent for a set of streaming
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* mode DMA translations after a transfer.
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*
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* The same as pci_dma_sync_single_* but for a scatter-gather list,
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* same rules and usage.
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*/
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extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
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/* Return whether the given PCI device DMA address mask can
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* be supported properly. For example, if your device can
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* only drive the low 24-bits during PCI bus mastering, then
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* you would pass 0x00ffffff as the mask to this function.
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*/
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extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
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{
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return 1;
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}
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#define pci_dac_dma_supported(dev, mask) (0)
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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*strat = PCI_DMA_BURST_INFINITY;
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*strategy_parameter = ~0UL;
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}
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static inline void pcibios_add_platform_entries(struct pci_dev *dev)
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{
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}
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#define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
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static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
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{
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return (dma_addr == PCI_DMA_ERROR_CODE);
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}
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#endif /* __KERNEL__ */
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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#endif /* __SPARC_PCI_H */
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