Nick Hu b71f312e9b riscv: Fix udelay in RV32. ... [ Upstream commit d0e1f2110a5eeb6e410b2dd37d98bc5b30da7bc7 ] In RV32, udelay would delay the wrong cycle. When it shifts right "UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works correctly in RV64. Because the 'ucycles' always needs to be 64 bits variable. Signed-off-by: Nick Hu <nickhu@andestech.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> [paul.walmsley@sifive.com: fixed minor spelling error] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2019-07-14 08:11:09 +02:00
..
delay.c	riscv: Fix udelay in RV32.	2019-07-14 08:11:09 +02:00
Makefile	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
memcpy.S
memset.S
tishift.S	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
uaccess.S	RISC-V: Make our port sparse-clean	2018-06-11 09:09:49 -07:00
udivdi3.S