d4b2bab4f2
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* pata_sil680.c - SIL680 PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* based upon
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*
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* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
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*
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* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat <alan@redhat.com>
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Documentation publically available.
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*
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* If you have strange problems with nVidia chipset systems please
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* see the SI support documentation and update your system BIOS
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* if neccessary
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*
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* TODO
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* If we know all our devices are LBA28 (or LBA28 sized) we could use
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* the command fifo mode.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_sil680"
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#define DRV_VERSION "0.4.6"
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/**
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* sil680_selreg - return register base
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* @hwif: interface
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* @r: config offset
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*
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* Turn a config register offset into the right address in either
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* PCI space or MMIO space to access the control register in question
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* Thankfully this is a configuration operation so isnt performance
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* criticial.
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*/
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static unsigned long sil680_selreg(struct ata_port *ap, int r)
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{
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unsigned long base = 0xA0 + r;
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base += (ap->port_no << 4);
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return base;
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}
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/**
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* sil680_seldev - return register base
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* @hwif: interface
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* @r: config offset
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*
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* Turn a config register offset into the right address in either
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* PCI space or MMIO space to access the control register in question
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* including accounting for the unit shift.
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*/
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static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
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{
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unsigned long base = 0xA0 + r;
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base += (ap->port_no << 4);
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base |= adev->devno ? 2 : 0;
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return base;
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}
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/**
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* sil680_cable_detect - cable detection
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* @ap: ATA port
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*
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* Perform cable detection. The SIL680 stores this in PCI config
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* space for us.
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*/
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static int sil680_cable_detect(struct ata_port *ap) {
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned long addr = sil680_selreg(ap, 0);
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u8 ata66;
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pci_read_config_byte(pdev, addr, &ata66);
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if (ata66 & 1)
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return ATA_CBL_PATA80;
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else
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return ATA_CBL_PATA40;
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}
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/**
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* sil680_bus_reset - reset the SIL680 bus
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* @ap: ATA port to reset
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* @deadline: deadline jiffies for the operation
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*
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* Perform the SIL680 housekeeping when doing an ATA bus reset
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*/
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static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes,
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unsigned long deadline)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned long addr = sil680_selreg(ap, 0);
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u8 reset;
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pci_read_config_byte(pdev, addr, &reset);
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pci_write_config_byte(pdev, addr, reset | 0x03);
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udelay(25);
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pci_write_config_byte(pdev, addr, reset);
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return ata_std_softreset(ap, classes, deadline);
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}
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static void sil680_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset);
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}
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/**
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* sil680_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the SIL680 registers for PIO mode. Note that the task speed
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* registers are shared between the devices so we must pick the lowest
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* mode for command work.
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*/
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static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
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static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
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unsigned long tfaddr = sil680_selreg(ap, 0x02);
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unsigned long addr = sil680_seldev(ap, adev, 0x04);
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unsigned long addr_mask = 0x80 + 4 * ap->port_no;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int pio = adev->pio_mode - XFER_PIO_0;
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int lowest_pio = pio;
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int port_shift = 4 * adev->devno;
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u16 reg;
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u8 mode;
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struct ata_device *pair = ata_dev_pair(adev);
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if (pair != NULL && adev->pio_mode > pair->pio_mode)
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lowest_pio = pair->pio_mode - XFER_PIO_0;
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pci_write_config_word(pdev, addr, speed_p[pio]);
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pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
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pci_read_config_word(pdev, tfaddr-2, ®);
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pci_read_config_byte(pdev, addr_mask, &mode);
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reg &= ~0x0200; /* Clear IORDY */
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mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
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if (ata_pio_need_iordy(adev)) {
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reg |= 0x0200; /* Enable IORDY */
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mode |= 1 << port_shift;
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}
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pci_write_config_word(pdev, tfaddr-2, reg);
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pci_write_config_byte(pdev, addr_mask, mode);
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}
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/**
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* sil680_set_dmamode - set initial DMA mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program the MWDMA/UDMA modes for the sil680 k
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* chipset. The MWDMA mode values are pulled from a lookup table
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* while the chipset uses mode number for UDMA.
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*/
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static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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static u8 ultra_table[2][7] = {
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{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
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{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
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};
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static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned long ma = sil680_seldev(ap, adev, 0x08);
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unsigned long ua = sil680_seldev(ap, adev, 0x0C);
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unsigned long addr_mask = 0x80 + 4 * ap->port_no;
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int port_shift = adev->devno * 4;
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u8 scsc, mode;
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u16 multi, ultra;
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pci_read_config_byte(pdev, 0x8A, &scsc);
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pci_read_config_byte(pdev, addr_mask, &mode);
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pci_read_config_word(pdev, ma, &multi);
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pci_read_config_word(pdev, ua, &ultra);
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/* Mask timing bits */
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ultra &= ~0x3F;
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mode &= ~(0x03 << port_shift);
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/* Extract scsc */
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scsc = (scsc & 0x30) ? 1: 0;
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if (adev->dma_mode >= XFER_UDMA_0) {
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multi = 0x10C1;
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ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
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mode |= (0x03 << port_shift);
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} else {
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multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
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mode |= (0x02 << port_shift);
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}
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pci_write_config_byte(pdev, addr_mask, mode);
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pci_write_config_word(pdev, ma, multi);
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pci_write_config_word(pdev, ua, ultra);
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}
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static struct scsi_host_template sil680_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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#ifdef CONFIG_PM
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.suspend = ata_scsi_device_suspend,
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.resume = ata_scsi_device_resume,
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#endif
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};
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static struct ata_port_operations sil680_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = sil680_set_piomode,
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.set_dmamode = sil680_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = sil680_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = sil680_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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/**
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* sil680_init_chip - chip setup
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* @pdev: PCI device
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*
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* Perform all the chip setup which must be done both when the device
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* is powered up on boot and when we resume in case we resumed from RAM.
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* Returns the final clock settings.
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*/
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static u8 sil680_init_chip(struct pci_dev *pdev)
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{
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u32 class_rev = 0;
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u8 tmpbyte = 0;
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pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
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class_rev &= 0xff;
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/* FIXME: double check */
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
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pci_write_config_byte(pdev, 0x80, 0x00);
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pci_write_config_byte(pdev, 0x84, 0x00);
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pci_read_config_byte(pdev, 0x8A, &tmpbyte);
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printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
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tmpbyte & 1, tmpbyte & 0x30);
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switch(tmpbyte & 0x30) {
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case 0x00:
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/* 133 clock attempt to force it on */
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pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
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break;
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case 0x30:
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/* if clocking is disabled */
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/* 133 clock attempt to force it on */
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pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
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break;
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case 0x10:
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/* 133 already */
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break;
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case 0x20:
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/* BIOS set PCI x2 clocking */
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break;
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}
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pci_read_config_byte(pdev, 0x8A, &tmpbyte);
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printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
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tmpbyte & 1, tmpbyte & 0x30);
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pci_write_config_byte(pdev, 0xA1, 0x72);
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pci_write_config_word(pdev, 0xA2, 0x328A);
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pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
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pci_write_config_dword(pdev, 0xA8, 0x43924392);
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pci_write_config_dword(pdev, 0xAC, 0x40094009);
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pci_write_config_byte(pdev, 0xB1, 0x72);
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pci_write_config_word(pdev, 0xB2, 0x328A);
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pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
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pci_write_config_dword(pdev, 0xB8, 0x43924392);
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pci_write_config_dword(pdev, 0xBC, 0x40094009);
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switch(tmpbyte & 0x30) {
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case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
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case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
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case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
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/* This last case is _NOT_ ok */
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case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
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}
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return tmpbyte & 0x30;
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}
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static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static struct ata_port_info info = {
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.sht = &sil680_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = 0x7f,
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.port_ops = &sil680_port_ops
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};
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static struct ata_port_info info_slow = {
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.sht = &sil680_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = 0x3f,
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.port_ops = &sil680_port_ops
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};
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static struct ata_port_info *port_info[2] = {&info, &info};
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static int printed_version;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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switch(sil680_init_chip(pdev))
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{
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case 0:
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port_info[0] = port_info[1] = &info_slow;
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break;
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case 0x30:
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return -ENODEV;
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}
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return ata_pci_init_one(pdev, port_info, 2);
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}
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#ifdef CONFIG_PM
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static int sil680_reinit_one(struct pci_dev *pdev)
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{
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sil680_init_chip(pdev);
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return ata_pci_device_resume(pdev);
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}
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#endif
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static const struct pci_device_id sil680[] = {
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{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
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{ },
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};
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static struct pci_driver sil680_pci_driver = {
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.name = DRV_NAME,
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.id_table = sil680,
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.probe = sil680_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = sil680_reinit_one,
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#endif
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};
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static int __init sil680_init(void)
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{
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return pci_register_driver(&sil680_pci_driver);
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}
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static void __exit sil680_exit(void)
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{
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pci_unregister_driver(&sil680_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for SI680 PATA");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sil680);
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MODULE_VERSION(DRV_VERSION);
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module_init(sil680_init);
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module_exit(sil680_exit);
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