ShihPo Hung a96ac5cb8a riscv: mm: synchronize MMU after pte change ... commit bf587caae305ae3b4393077fb22c98478ee55755 upstream. Because RISC-V compliant implementations can cache invalid entries in TLB, an SFENCE.VMA is necessary after changes to the page table. This patch adds an SFENCE.vma for the vmalloc_fault path. Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com> [paul.walmsley@sifive.com: reversed tab->whitespace conversion, wrapped comment lines] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: linux-riscv@lists.infradead.org Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-06-25 11:36:00 +08:00
..
cacheflush.c	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00
extable.c
fault.c	riscv: mm: synchronize MMU after pte change	2019-06-25 11:36:00 +08:00
init.c	riscv: fixup max_low_pfn with PFN_DOWN.	2019-03-13 14:02:27 -07:00
ioremap.c	RISC-V: io.h: type fixes for warnings	2017-11-30 10:01:10 -08:00
Makefile	RISC-V: Flush I$ when making a dirty page executable	2017-11-30 12:58:25 -08:00