b445e26cbf
In particular, avoid membar instructions in the delay slot of a jmpl instruction. UltraSPARC-I, II, IIi, and IIe have a bug, documented in the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51 The long and short of it is that if the IMU unit misses on a branch or jmpl, and there is a store buffer synchronizing membar in the delay slot, the chip can stop fetching instructions. If interrupts are enabled or some other trap is enabled, the chip will unwedge itself, but performance will suffer. We already had a workaround for this bug in a few spots, but it's better to have the entire tree sanitized for this rule. Signed-off-by: David S. Miller <davem@davemloft.net>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/* $Id: rwsem.h,v 1.5 2001/11/18 00:12:56 davem Exp $
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* rwsem.h: R/W semaphores implemented using CAS
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*
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* Written by David S. Miller (davem@redhat.com), 2001.
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* Derived from asm-i386/rwsem.h
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*/
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#ifndef _SPARC64_RWSEM_H
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#define _SPARC64_RWSEM_H
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#ifndef _LINUX_RWSEM_H
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#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
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#endif
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#ifdef __KERNEL__
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <asm/rwsem-const.h>
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struct rwsem_waiter;
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struct rw_semaphore {
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signed int count;
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spinlock_t wait_lock;
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struct list_head wait_list;
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};
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#define __RWSEM_INITIALIZER(name) \
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{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) }
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#define DECLARE_RWSEM(name) \
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struct rw_semaphore name = __RWSEM_INITIALIZER(name)
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static __inline__ void init_rwsem(struct rw_semaphore *sem)
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{
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sem->count = RWSEM_UNLOCKED_VALUE;
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spin_lock_init(&sem->wait_lock);
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INIT_LIST_HEAD(&sem->wait_list);
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}
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extern void __down_read(struct rw_semaphore *sem);
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extern int __down_read_trylock(struct rw_semaphore *sem);
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extern void __down_write(struct rw_semaphore *sem);
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extern int __down_write_trylock(struct rw_semaphore *sem);
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extern void __up_read(struct rw_semaphore *sem);
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extern void __up_write(struct rw_semaphore *sem);
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extern void __downgrade_write(struct rw_semaphore *sem);
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static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
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{
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int tmp = delta;
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__asm__ __volatile__(
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"1:\tlduw [%2], %%g1\n\t"
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"add %%g1, %1, %%g7\n\t"
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"cas [%2], %%g1, %%g7\n\t"
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"cmp %%g1, %%g7\n\t"
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"membar #StoreLoad | #StoreStore\n\t"
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"bne,pn %%icc, 1b\n\t"
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" nop\n\t"
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"mov %%g7, %0\n\t"
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: "=&r" (tmp)
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: "0" (tmp), "r" (sem)
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: "g1", "g7", "memory", "cc");
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return tmp + delta;
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}
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#define rwsem_atomic_add rwsem_atomic_update
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static __inline__ __u16 rwsem_cmpxchgw(struct rw_semaphore *sem, __u16 __old, __u16 __new)
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{
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u32 old = (sem->count & 0xffff0000) | (u32) __old;
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u32 new = (old & 0xffff0000) | (u32) __new;
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u32 prev;
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again:
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__asm__ __volatile__("cas [%2], %3, %0\n\t"
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"membar #StoreLoad | #StoreStore"
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: "=&r" (prev)
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: "0" (new), "r" (sem), "r" (old)
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: "memory");
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/* To give the same semantics as x86 cmpxchgw, keep trying
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* if only the upper 16-bits changed.
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*/
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if (prev != old &&
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((prev & 0xffff) == (old & 0xffff)))
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goto again;
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return prev & 0xffff;
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}
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static __inline__ signed long rwsem_cmpxchg(struct rw_semaphore *sem, signed long old, signed long new)
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{
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return cmpxchg(&sem->count,old,new);
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}
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#endif /* __KERNEL__ */
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#endif /* _SPARC64_RWSEM_H */
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