Nick Hu b71f312e9b riscv: Fix udelay in RV32. ... [ Upstream commit d0e1f2110a5eeb6e410b2dd37d98bc5b30da7bc7 ] In RV32, udelay would delay the wrong cycle. When it shifts right "UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works correctly in RV64. Because the 'ucycles' always needs to be 64 bits variable. Signed-off-by: Nick Hu <nickhu@andestech.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> [paul.walmsley@sifive.com: fixed minor spelling error] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2019-07-14 08:11:09 +02:00
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configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	riscv: fix accessing 8-byte variable from RV32	2019-05-08 07:21:47 +02:00
kernel	riscv: fixup max_low_pfn with PFN_DOWN.	2019-03-13 14:02:27 -07:00
lib	riscv: Fix udelay in RV32.	2019-07-14 08:11:09 +02:00
mm	riscv: mm: synchronize MMU after pte change	2019-06-25 11:36:00 +08:00
Kconfig	kconfig: include kernel/Kconfig.preempt from init/Kconfig	2018-08-02 08:06:54 +09:00
Kconfig.debug	Kconfig: consolidate the "Kernel hacking" menu	2018-08-02 08:06:48 +09:00
Makefile	riscv: add missing vdso_install target	2018-12-01 09:37:33 +01:00