da748e58a9
Clearing dim layers indiscriminately for each blend stage on each commit wastes a lot of CPU time since the clearing process is heavy on register accesses. We can optimize this by only clearing dim layers when they're actually set, and only clearing them on a per-stage basis at that. This reduces display commit latency considerably. Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com> |
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