6eb9b4a36d
[ Upstream commit c775cbf62ed4911e4f0f23880f01815753123690 ]
The MCLK of the WM8731 on the AT91SAM9G20-EK board is connected to the
PCK0 output of the SoC, intended in the reference software to be supplied
using PLLB and programmed to 12MHz. As originally written for use with a
board file the audio driver was responsible for configuring the entire tree
but in the conversion to the common clock framework the registration of
the named pck0 and pllb clocks was removed so the driver has failed to
instantiate ever since.
Since the WM8731 driver has had support for managing a MCLK provided via
the common clock framework for some time we can simply drop all the clock
management code from the machine driver other than configuration of the
sysclk rate, the CODEC driver still respects that configuration from the
machine driver.
Fixes:
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|---|---|---|
| .. | ||
| atmel_ssc_dai.c | ||
| atmel_ssc_dai.h | ||
| atmel_wm8904.c | ||
| atmel-classd.c | ||
| atmel-classd.h | ||
| atmel-i2s.c | ||
| atmel-pcm-dma.c | ||
| atmel-pcm-pdc.c | ||
| atmel-pcm.h | ||
| atmel-pdmic.c | ||
| atmel-pdmic.h | ||
| Kconfig | ||
| Makefile | ||
| sam9g20_wm8731.c | ||
| sam9x5_wm8731.c | ||
| tse850-pcm5142.c | ||