285f5fa7e9
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* linux/include/asm-arm/arch-iop13xx/system.h
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*
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/arch/iop13xx.h>
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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}
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/* WDTCR CP6 R7 Page 9 */
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static inline u32 read_wdtcr(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
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return val;
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}
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static inline void write_wdtcr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
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}
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/* WDTSR CP6 R8 Page 9 */
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static inline u32 read_wdtsr(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
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return val;
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}
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static inline void write_wdtsr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
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}
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#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
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#define IOP13XX_WDTCR_EN 0xe1e1e1e1
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#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
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#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
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#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
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#define IOP13XX_WDTCR_IB_RESET (1 << 0)
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static inline void arch_reset(char mode)
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{
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/*
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* Reset the internal bus (warning both cores are reset)
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*/
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u32 cp_flags = iop13xx_cp6_save();
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write_wdtcr(IOP13XX_WDTCR_EN_ARM);
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write_wdtcr(IOP13XX_WDTCR_EN);
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write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
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write_wdtcr(0x1000);
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iop13xx_cp6_restore(cp_flags);
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for(;;);
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}
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