Dinh Nguyen a8f7703f22 clk: socfpga: stratix10: fix rate caclulationg for cnt_clks ... commit c7ec75ea4d5316518adc87224e3cff47192579e7 upstream. Checking bypass_reg is incorrect for calculating the cnt_clk rates. Instead we should be checking that there is a proper hardware register that holds the clock divider. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-08-29 08:28:49 +02:00
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clk-gate-a10.c
clk-gate-s10.c
clk-gate.c
clk-periph-a10.c
clk-periph-s10.c
clk-periph.c
clk-pll-a10.c
clk-pll-s10.c
clk-pll.c
clk-s10.c
clk.c
clk.h
Makefile
stratix10-clk.h