Zihao Yu 4f17a45f8e riscv,entry: fix misaligned base for excp_vect_table ... [ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ] In RV64, the size of each entry in excp_vect_table is 8 bytes. If the base of the table is not 8-byte aligned, loading an entry in the table will raise a misaligned exception. Although such exception will be handled by opensbi/bbl, this still causes performance degradation. Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-04-16 11:49:30 +02:00
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configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	riscv: virt_addr_valid must check the address belongs to linear mapping	2021-02-23 15:00:56 +01:00
kernel	riscv,entry: fix misaligned base for excp_vect_table	2021-04-16 11:49:30 +02:00
lib	riscv: Fix udelay in RV32.	2019-07-14 08:11:09 +02:00
mm	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	2019-12-01 09:16:53 +01:00
Kconfig	kconfig: include kernel/Kconfig.preempt from init/Kconfig	2018-08-02 08:06:54 +09:00
Kconfig.debug	Kconfig: consolidate the "Kernel hacking" menu	2018-08-02 08:06:48 +09:00
Makefile	riscv: add missing vdso_install target	2018-12-01 09:37:33 +01:00