Russell King 95f3df6bcb [ARM] Fix SA110/SA1100 cache flushing ... We had two implementations for flushing the cache, which meant StrongARM caches weren't being correctly flushed. Fix this by always using the v4wb_flush_kern_cache_all method, rather than duplicating it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2006-04-07 13:23:57 +01:00
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abort-ev4.S
abort-ev4t.S
abort-ev5t.S
abort-ev5tj.S
abort-ev6.S
abort-lv4t.S
abort-macro.S
alignment.c
cache-v3.S
cache-v4.S
cache-v4wb.S	[ARM] Fix SA110/SA1100 cache flushing	2006-04-07 13:23:57 +01:00
cache-v4wt.S
cache-v6.S
consistent.c	[ARM] 3439/2: xsc3: add I/O coherency support	2006-04-02 00:07:39 +01:00
copypage-v3.S
copypage-v4mc.c
copypage-v4wb.S
copypage-v4wt.S
copypage-v6.c
copypage-xsc3.S	[ARM] 3377/2: add support for intel xsc3 core	2006-03-28 21:00:40 +01:00
copypage-xscale.c
discontig.c
extable.c
fault-armv.c
fault.c
fault.h
flush.c
init.c	[ARM] Move FLUSH_BASE macros to asm/arch/memory.h	2006-04-07 13:22:21 +01:00
ioremap.c
Kconfig	[ARM] 3377/2: add support for intel xsc3 core	2006-03-28 21:00:40 +01:00
Makefile	[ARM] 3377/2: add support for intel xsc3 core	2006-03-28 21:00:40 +01:00
mm-armv.c	[ARM] 3439/2: xsc3: add I/O coherency support	2006-04-02 00:07:39 +01:00
mmap.c
mmu.c
proc-arm6_7.S
proc-arm720.S
proc-arm920.S
proc-arm922.S
proc-arm925.S
proc-arm926.S
proc-arm1020.S
proc-arm1020e.S
proc-arm1022.S
proc-arm1026.S
proc-macros.S
proc-sa110.S	[ARM] Fix SA110/SA1100 cache flushing	2006-04-07 13:23:57 +01:00
proc-sa1100.S	[ARM] Fix SA110/SA1100 cache flushing	2006-04-07 13:23:57 +01:00
proc-syms.c
proc-v6.S	[ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.	2006-03-27 16:59:07 +01:00
proc-xsc3.S	[ARM] 3439/2: xsc3: add I/O coherency support	2006-04-02 00:07:39 +01:00
proc-xscale.S
tlb-v3.S
tlb-v4.S
tlb-v4wb.S
tlb-v4wbi.S
tlb-v6.S