d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
256 lines
6.1 KiB
C
256 lines
6.1 KiB
C
/*
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* Programmable Interrupt Controller functions for the Freescale MPC52xx
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* embedded CPU.
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*
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*
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* Maintainer : Sylvain Munaut <tnt@246tNt.com>
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*
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* Based on (well, mostly copied from) the code from the 2.4 kernel by
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* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Montavista Software, Inc
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/stddef.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/mpc52xx.h>
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static struct mpc52xx_intr __iomem *intr;
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static struct mpc52xx_sdma __iomem *sdma;
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static void
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mpc52xx_ic_disable(unsigned int irq)
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{
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u32 val;
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if (irq == MPC52xx_IRQ0) {
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val = in_be32(&intr->ctrl);
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val &= ~(1 << 11);
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out_be32(&intr->ctrl, val);
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}
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else if (irq < MPC52xx_IRQ1) {
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BUG();
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}
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else if (irq <= MPC52xx_IRQ3) {
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val = in_be32(&intr->ctrl);
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val &= ~(1 << (10 - (irq - MPC52xx_IRQ1)));
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out_be32(&intr->ctrl, val);
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}
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else if (irq < MPC52xx_SDMA_IRQ_BASE) {
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val = in_be32(&intr->main_mask);
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val |= 1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE));
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out_be32(&intr->main_mask, val);
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}
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else if (irq < MPC52xx_PERP_IRQ_BASE) {
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val = in_be32(&sdma->IntMask);
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val |= 1 << (irq - MPC52xx_SDMA_IRQ_BASE);
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out_be32(&sdma->IntMask, val);
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}
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else {
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val = in_be32(&intr->per_mask);
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val |= 1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE));
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out_be32(&intr->per_mask, val);
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}
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}
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static void
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mpc52xx_ic_enable(unsigned int irq)
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{
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u32 val;
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if (irq == MPC52xx_IRQ0) {
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val = in_be32(&intr->ctrl);
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val |= 1 << 11;
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out_be32(&intr->ctrl, val);
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}
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else if (irq < MPC52xx_IRQ1) {
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BUG();
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}
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else if (irq <= MPC52xx_IRQ3) {
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val = in_be32(&intr->ctrl);
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val |= 1 << (10 - (irq - MPC52xx_IRQ1));
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out_be32(&intr->ctrl, val);
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}
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else if (irq < MPC52xx_SDMA_IRQ_BASE) {
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val = in_be32(&intr->main_mask);
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val &= ~(1 << (16 - (irq - MPC52xx_MAIN_IRQ_BASE)));
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out_be32(&intr->main_mask, val);
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}
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else if (irq < MPC52xx_PERP_IRQ_BASE) {
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val = in_be32(&sdma->IntMask);
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val &= ~(1 << (irq - MPC52xx_SDMA_IRQ_BASE));
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out_be32(&sdma->IntMask, val);
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}
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else {
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val = in_be32(&intr->per_mask);
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val &= ~(1 << (31 - (irq - MPC52xx_PERP_IRQ_BASE)));
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out_be32(&intr->per_mask, val);
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}
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}
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static void
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mpc52xx_ic_ack(unsigned int irq)
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{
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u32 val;
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/*
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* Only some irqs are reset here, others in interrupting hardware.
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*/
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switch (irq) {
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case MPC52xx_IRQ0:
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val = in_be32(&intr->ctrl);
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val |= 0x08000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC52xx_CCS_IRQ:
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val = in_be32(&intr->enc_status);
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val |= 0x00000400;
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out_be32(&intr->enc_status, val);
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break;
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case MPC52xx_IRQ1:
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val = in_be32(&intr->ctrl);
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val |= 0x04000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC52xx_IRQ2:
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val = in_be32(&intr->ctrl);
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val |= 0x02000000;
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out_be32(&intr->ctrl, val);
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break;
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case MPC52xx_IRQ3:
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val = in_be32(&intr->ctrl);
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val |= 0x01000000;
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out_be32(&intr->ctrl, val);
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break;
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default:
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if (irq >= MPC52xx_SDMA_IRQ_BASE
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&& irq < (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)) {
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out_be32(&sdma->IntPend,
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1 << (irq - MPC52xx_SDMA_IRQ_BASE));
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}
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break;
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}
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}
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static void
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mpc52xx_ic_disable_and_ack(unsigned int irq)
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{
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mpc52xx_ic_disable(irq);
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mpc52xx_ic_ack(irq);
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}
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static void
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mpc52xx_ic_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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mpc52xx_ic_enable(irq);
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}
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static struct hw_interrupt_type mpc52xx_ic = {
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.typename = " MPC52xx ",
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.enable = mpc52xx_ic_enable,
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.disable = mpc52xx_ic_disable,
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.ack = mpc52xx_ic_disable_and_ack,
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.end = mpc52xx_ic_end,
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};
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void __init
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mpc52xx_init_irq(void)
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{
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int i;
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u32 intr_ctrl;
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/* Remap the necessary zones */
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intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
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sdma = ioremap(MPC52xx_PA(MPC52xx_SDMA_OFFSET), MPC52xx_SDMA_SIZE);
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if ((intr==NULL) || (sdma==NULL))
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panic("Can't ioremap PIC/SDMA register for init_irq !");
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/* Disable all interrupt sources. */
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out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
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out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
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out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
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out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
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intr_ctrl = in_be32(&intr->ctrl);
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intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
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intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
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0x00001000 | /* MEE master external enable */
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0x00000000 | /* 0 means disable IRQ 0-3 */
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0x00000001; /* CEb route critical normally */
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out_be32(&intr->ctrl, intr_ctrl);
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/* Zero a bunch of the priority settings. */
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out_be32(&intr->per_pri1, 0);
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out_be32(&intr->per_pri2, 0);
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out_be32(&intr->per_pri3, 0);
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out_be32(&intr->main_pri1, 0);
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out_be32(&intr->main_pri2, 0);
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/* Initialize irq_desc[i].chip's with mpc52xx_ic. */
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for (i = 0; i < NR_IRQS; i++) {
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irq_desc[i].chip = &mpc52xx_ic;
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irq_desc[i].status = IRQ_LEVEL;
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}
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#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
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for (i=0 ; i<4 ; i++) {
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int mode;
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mode = IRQn_MODE(intr_ctrl,i);
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if ((mode == 0x1) || (mode == 0x2))
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irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
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}
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}
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int
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mpc52xx_get_irq(struct pt_regs *regs)
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{
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u32 status;
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int irq = -1;
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status = in_be32(&intr->enc_status);
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if (status & 0x00000400) { /* critical */
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irq = (status >> 8) & 0x3;
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if (irq == 2) /* high priority peripheral */
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goto peripheral;
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irq += MPC52xx_CRIT_IRQ_BASE;
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}
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else if (status & 0x00200000) { /* main */
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irq = (status >> 16) & 0x1f;
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if (irq == 4) /* low priority peripheral */
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goto peripheral;
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irq += MPC52xx_MAIN_IRQ_BASE;
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}
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else if (status & 0x20000000) { /* peripheral */
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peripheral:
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irq = (status >> 24) & 0x1f;
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if (irq == 0) { /* bestcomm */
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status = in_be32(&sdma->IntPend);
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irq = ffs(status) + MPC52xx_SDMA_IRQ_BASE-1;
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}
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else
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irq += MPC52xx_PERP_IRQ_BASE;
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}
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return irq;
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}
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