0bb3184df5
Trival patch for CPU hotplug. In CPU identify part, only did cleaup for intel CPUs. Need do for other CPUs if they support S3 SMP. Signed-off-by: Li Shaohua<shaohua.li@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/*
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* P5 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@redhat.com>
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include "mce.h"
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/* Machine check handler for Pentium class Intel */
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static fastcall void pentium_machine_check(struct pt_regs * regs, long error_code)
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{
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u32 loaddr, hi, lotype;
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
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if(lotype&(1<<5))
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printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* Set up machine check reporting for processors with Intel style MCE */
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void __devinit intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/*Check for MCE support */
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if( !cpu_has(c, X86_FEATURE_MCE) )
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return;
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/* Default P5 to off as its often misconnected */
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if(mce_disabled != -1)
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return;
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machine_check_vector = pentium_machine_check;
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wmb();
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/* Read registers before enabling */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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printk(KERN_INFO "Intel old style machine check architecture supported.\n");
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/* Enable MCE */
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set_in_cr4(X86_CR4_MCE);
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printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
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}
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