320 lines
8.3 KiB
C
320 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.*/
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#ifndef __MSM_PCIE_H
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#define __MSM_PCIE_H
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#include <linux/types.h>
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#include <linux/pci.h>
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enum msm_pcie_config {
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MSM_PCIE_CONFIG_INVALID = 0,
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MSM_PCIE_CONFIG_NO_CFG_RESTORE = 0x1,
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MSM_PCIE_CONFIG_LINKDOWN = 0x2,
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MSM_PCIE_CONFIG_NO_RECOVERY = 0x4,
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MSM_PCIE_CONFIG_NO_L1SS_TO = 0x8,
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};
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enum msm_pcie_pm_opt {
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MSM_PCIE_DRV_SUSPEND,
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MSM_PCIE_SUSPEND,
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MSM_PCIE_RESUME,
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MSM_PCIE_DISABLE_PC,
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MSM_PCIE_ENABLE_PC,
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MSM_PCIE_HANDLE_LINKDOWN,
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};
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enum msm_pcie_event {
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MSM_PCIE_EVENT_INVALID = 0,
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MSM_PCIE_EVENT_LINKDOWN = 0x1,
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MSM_PCIE_EVENT_LINKUP = 0x2,
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MSM_PCIE_EVENT_WAKEUP = 0x4,
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MSM_PCIE_EVENT_L1SS_TIMEOUT = BIT(3),
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MSM_PCIE_EVENT_DRV_CONNECT = BIT(4),
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MSM_PCIE_EVENT_DRV_DISCONNECT = BIT(5),
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MSM_PCIE_EVENT_LINK_RECOVER = BIT(6),
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};
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enum msm_pcie_trigger {
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MSM_PCIE_TRIGGER_CALLBACK,
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MSM_PCIE_TRIGGER_COMPLETION,
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};
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struct msm_pcie_notify {
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enum msm_pcie_event event;
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void *user;
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void *data;
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u32 options;
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};
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struct msm_pcie_register_event {
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u32 events;
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void *user;
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enum msm_pcie_trigger mode;
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void (*callback)(struct msm_pcie_notify *notify);
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struct msm_pcie_notify notify;
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struct completion *completion;
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u32 options;
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};
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#ifdef CONFIG_PCI_MSM_MSI
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int msm_msi_init(struct device *dev);
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#else
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static inline int msm_msi_init(struct device *dev)
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{
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return -EINVAL;
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}
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#endif
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#ifdef CONFIG_PCI_MSM
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/**
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* msm_pcie_set_target_link_speed - sets the maximum GEN speed PCIe can link up
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* with
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* @rc_idx: root complex port number that endpoint is connected to
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* @target_link_speed: maximum GEN speed PCIe can link up with
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*
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* Provide PCIe clients the option to control which maximum GEN speed PCIe
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* can link up with. Clients may choose only GEN speed within root complex's
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* controller capability or up to what is defined in devicetree,
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* qcom,target-link-speed.
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*
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* Client may also pass 0 for target_link_speed to have
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* PCIe root complex reset and use the default maximum GEN speed.
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*
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* Return 0 on success, negative value on error
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*/
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int msm_pcie_set_target_link_speed(u32 rc_idx, u32 target_link_speed);
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/**
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* msm_pcie_allow_l1 - allow PCIe link to re-enter L1
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* @pci_dev: client's pci device structure
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*
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* This function gives PCIe clients the control to allow the link to re-enter
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* L1. Should only be used after msm_pcie_prevent_l1 has been called.
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*/
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void msm_pcie_allow_l1(struct pci_dev *pci_dev);
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/**
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* msm_pcie_prevent_l1 - keeps PCIe link out of L1
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* @pci_dev: client's pci device structure
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*
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* This function gives PCIe clients the control to exit and prevent the link
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* from entering L1.
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*
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* Return 0 on success, negative value on error
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*/
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int msm_pcie_prevent_l1(struct pci_dev *pci_dev);
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/**
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* msm_pcie_set_link_bandwidth - updates the number of lanes and speed of PCIe
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* link.
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* @pci_dev: client's pci device structure
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* @target_link_speed: gen speed
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* @target_link_width: number of lanes
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*
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* This function gives PCIe clients the control to update the number of lanes
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* and gen speed of the link.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_set_link_bandwidth(struct pci_dev *pci_dev, u16 target_link_speed,
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u16 target_link_width);
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/**
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* msm_pcie_l1ss_timeout_disable - disable L1ss timeout feature
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* @pci_dev: client's pci device structure
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*
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* This function gives PCIe clients the control to disable L1ss timeout
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* feature.
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*/
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void msm_pcie_l1ss_timeout_disable(struct pci_dev *pci_dev);
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/**
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* msm_pcie_l1ss_timeout_enable - enable L1ss timeout feature
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* @pci_dev: client's pci device structure
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*
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* This function gives PCIe clients the control to enable L1ss timeout
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* feature.
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*/
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void msm_pcie_l1ss_timeout_enable(struct pci_dev *pci_dev);
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/**
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* msm_pcie_pm_control - control the power state of a PCIe link.
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* @pm_opt: power management operation
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* @busnr: bus number of PCIe endpoint
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* @user: handle of the caller
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* @data: private data from the caller
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* @options: options for pm control
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*
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* This function gives PCIe endpoint device drivers the control to change
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* the power state of a PCIe link for their device.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr, void *user,
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void *data, u32 options);
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/**
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* msm_pcie_register_event - register an event with PCIe bus driver.
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* @reg: event structure
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*
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* This function gives PCIe endpoint device drivers an option to register
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* events with PCIe bus driver.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_register_event(struct msm_pcie_register_event *reg);
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/**
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* msm_pcie_deregister_event - deregister an event with PCIe bus driver.
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* @reg: event structure
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*
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* This function gives PCIe endpoint device drivers an option to deregister
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* events with PCIe bus driver.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_deregister_event(struct msm_pcie_register_event *reg);
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/**
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* msm_pcie_recover_config - recover config space.
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* @dev: pci device structure
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*
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* This function recovers the config space of both RC and Endpoint.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_recover_config(struct pci_dev *dev);
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/**
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* msm_pcie_enumerate - enumerate Endpoints.
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* @rc_idx: RC that Endpoints connect to.
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*
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* This function enumerates Endpoints connected to RC.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_enumerate(u32 rc_idx);
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/**
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* msm_pcie_recover_config - recover config space.
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* @dev: pci device structure
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*
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* This function recovers the config space of both RC and Endpoint.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_recover_config(struct pci_dev *dev);
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/**
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* msm_pcie_shadow_control - control the shadowing of PCIe config space.
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* @dev: pci device structure
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* @enable: shadowing should be enabled or disabled
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*
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* This function gives PCIe endpoint device drivers the control to enable
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* or disable the shadowing of PCIe config space.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_shadow_control(struct pci_dev *dev, bool enable);
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/*
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* msm_pcie_debug_info - run a PCIe specific debug testcase.
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* @dev: pci device structure
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* @option: specifies which PCIe debug testcase to execute
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* @base: PCIe specific range
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* @offset: offset of destination register
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* @mask: mask the bit(s) of destination register
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* @value: value to be written to destination register
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*
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* This function gives PCIe endpoint device drivers the control to
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* run a debug testcase.
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*
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* Return: 0 on success, negative value on error
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*/
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int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
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u32 offset, u32 mask, u32 value);
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/*
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* msm_pcie_reg_dump - dump pcie regsters for debug
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* @pci_dev: pci device structure
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* @buffer: destination buffer address
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* @len: length of buffer
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*
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* This functions dumps PCIE registers for debug. Sould be used when
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* link is alredy enabled
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*/
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int msm_pcie_reg_dump(struct pci_dev *pci_dev, u8 *buff, u32 len);
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#else /* !CONFIG_PCI_MSM */
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static inline int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr,
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void *user, void *data, u32 options)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_set_target_link_speed(u32 rc_idx,
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u32 target_link_speed)
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{
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return -ENODEV;
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}
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static inline void msm_pcie_allow_l1(struct pci_dev *pci_dev)
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{
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}
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static inline int msm_pcie_prevent_l1(struct pci_dev *pci_dev)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_l1ss_timeout_disable(struct pci_dev *pci_dev)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_l1ss_timeout_enable(struct pci_dev *pci_dev)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_register_event(struct msm_pcie_register_event *reg)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_deregister_event(struct msm_pcie_register_event *reg)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_recover_config(struct pci_dev *dev)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_enumerate(u32 rc_idx)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_shadow_control(struct pci_dev *dev, bool enable)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
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u32 offset, u32 mask, u32 value)
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{
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return -ENODEV;
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}
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static inline int msm_pcie_reg_dump(struct pci_dev *pci_dev, u8 *buff, u32 len)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_PCI_MSM */
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#endif /* __MSM_PCIE_H */
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