aba206738e
Add macro definitions in a dt-bindings header file for all the QMP USB DP register offsets. Change-Id: Ie7df8401d716544d36e637ea524ed0d946f8a042 Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
644 lines
32 KiB
C
644 lines
32 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H
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#define _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H
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#define USB3PHY_QSERDES_COM_ATB_SEL1 0x0000
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#define USB3PHY_QSERDES_COM_ATB_SEL2 0x0004
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#define USB3PHY_QSERDES_COM_FREQ_UPDATE 0x0008
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#define USB3PHY_QSERDES_COM_BG_TIMER 0x000C
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#define USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x0010
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#define USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
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#define USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
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#define USB3PHY_QSERDES_COM_SSC_PER1 0x001C
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#define USB3PHY_QSERDES_COM_SSC_PER2 0x0020
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#define USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
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#define USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
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#define USB3PHY_QSERDES_COM_POST_DIV 0x002C
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#define USB3PHY_QSERDES_COM_POST_DIV_MUX 0x0030
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#define USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034
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#define USB3PHY_QSERDES_COM_CLK_ENABLE1 0x0038
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#define USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x003C
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#define USB3PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040
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#define USB3PHY_QSERDES_COM_PLL_EN 0x0044
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#define USB3PHY_QSERDES_COM_PLL_IVCO 0x0048
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#define USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x004C
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#define USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x0050
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#define USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x0054
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#define USB3PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x0058
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#define USB3PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x005C
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#define USB3PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x0060
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#define USB3PHY_QSERDES_COM_CMN_RSVD0 0x0064
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#define USB3PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x0068
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#define USB3PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x006C
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#define USB3PHY_QSERDES_COM_BG_TRIM 0x0070
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#define USB3PHY_QSERDES_COM_CLK_EP_DIV 0x0074
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#define USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0078
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#define USB3PHY_QSERDES_COM_CP_CTRL_MODE1 0x007C
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#define USB3PHY_QSERDES_COM_CMN_RSVD1 0x0080
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#define USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x0084
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#define USB3PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x0088
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#define USB3PHY_QSERDES_COM_CMN_RSVD2 0x008C
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#define USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x0090
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#define USB3PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x0094
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#define USB3PHY_QSERDES_COM_CMN_RSVD3 0x0098
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#define USB3PHY_QSERDES_COM_PLL_CNTRL 0x009C
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#define USB3PHY_QSERDES_COM_PHASE_SEL_CTRL 0x00A0
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#define USB3PHY_QSERDES_COM_PHASE_SEL_DC 0x00A4
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#define USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x00A8
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#define USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x00AC
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#define USB3PHY_QSERDES_COM_CML_SYSCLK_SEL 0x00B0
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#define USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00B4
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#define USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x00B8
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#define USB3PHY_QSERDES_COM_RESTRIM_CTRL 0x00BC
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#define USB3PHY_QSERDES_COM_RESTRIM_CTRL2 0x00C0
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#define USB3PHY_QSERDES_COM_RESCODE_DIV_NUM 0x00C4
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#define USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00C8
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#define USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00CC
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#define USB3PHY_QSERDES_COM_DEC_START_MODE0 0x00D0
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#define USB3PHY_QSERDES_COM_DEC_START_MODE1 0x00D4
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#define USB3PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x00D8
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x00DC
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x00E0
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x00E4
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x00E8
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00EC
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#define USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x00F0
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#define USB3PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x00F4
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#define USB3PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x00F8
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#define USB3PHY_QSERDES_COM_CMN_RSVD4 0x00FC
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#define USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x0100
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#define USB3PHY_QSERDES_COM_INTEGLOOP_EN 0x0104
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#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x0108
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#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x010C
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#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x0110
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#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x0114
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#define USB3PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x0118
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#define USB3PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x011C
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#define USB3PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x0120
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#define USB3PHY_QSERDES_COM_VCO_TUNE_CTRL 0x0124
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#define USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x0128
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#define USB3PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x012C
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#define USB3PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x0130
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#define USB3PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x0134
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#define USB3PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x0138
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#define USB3PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x013C
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#define USB3PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x0140
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#define USB3PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x0144
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#define USB3PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x0148
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#define USB3PHY_QSERDES_COM_SAR 0x014C
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#define USB3PHY_QSERDES_COM_SAR_CLK 0x0150
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#define USB3PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x0154
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#define USB3PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x0158
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#define USB3PHY_QSERDES_COM_CMN_STATUS 0x015C
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#define USB3PHY_QSERDES_COM_RESET_SM_STATUS 0x0160
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#define USB3PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x0164
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#define USB3PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x0168
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#define USB3PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x016C
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#define USB3PHY_QSERDES_COM_BG_CTRL 0x0170
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#define USB3PHY_QSERDES_COM_CLK_SELECT 0x0174
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#define USB3PHY_QSERDES_COM_HSCLK_SEL 0x0178
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#define USB3PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x017C
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#define USB3PHY_QSERDES_COM_PLL_ANALOG 0x0180
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#define USB3PHY_QSERDES_COM_CORECLK_DIV 0x0184
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#define USB3PHY_QSERDES_COM_SW_RESET 0x0188
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#define USB3PHY_QSERDES_COM_CORE_CLK_EN 0x018C
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#define USB3PHY_QSERDES_COM_C_READY_STATUS 0x0190
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#define USB3PHY_QSERDES_COM_CMN_CONFIG 0x0194
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#define USB3PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x0198
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#define USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x019C
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#define USB3PHY_QSERDES_COM_DEBUG_BUS0 0x01A0
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#define USB3PHY_QSERDES_COM_DEBUG_BUS1 0x01A4
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#define USB3PHY_QSERDES_COM_DEBUG_BUS2 0x01A8
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#define USB3PHY_QSERDES_COM_DEBUG_BUS3 0x01AC
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#define USB3PHY_QSERDES_COM_DEBUG_BUS_SEL 0x01B0
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#define USB3PHY_QSERDES_COM_CMN_MISC1 0x01B4
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#define USB3PHY_QSERDES_COM_CMN_MISC2 0x01B8
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#define USB3PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x01BC
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#define USB3PHY_QSERDES_COM_CMN_RSVD5 0x01C0
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#define USB3PHY_QSERDES_TXA_BIST_MODE_LANENO 0x0200
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#define USB3PHY_QSERDES_TXA_BIST_INVERT 0x0204
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#define USB3PHY_QSERDES_TXA_CLKBUF_ENABLE 0x0208
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#define USB3PHY_QSERDES_TXA_TX_EMP_POST1_LVL 0x020C
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#define USB3PHY_QSERDES_TXA_TX_POST2_EMPH 0x0210
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#define USB3PHY_QSERDES_TXA_TX_BOOST_LVL_UP_DN 0x0214
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#define USB3PHY_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x0218
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#define USB3PHY_QSERDES_TXA_TX_DRV_LVL 0x021C
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#define USB3PHY_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x0220
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#define USB3PHY_QSERDES_TXA_RESET_TSYNC_EN 0x0224
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#define USB3PHY_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x0228
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#define USB3PHY_QSERDES_TXA_TX_BAND 0x022C
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#define USB3PHY_QSERDES_TXA_SLEW_CNTL 0x0230
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#define USB3PHY_QSERDES_TXA_INTERFACE_SELECT 0x0234
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#define USB3PHY_QSERDES_TXA_LPB_EN 0x0238
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#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_TX 0x023C
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#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_RX 0x0240
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#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x0244
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#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0248
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#define USB3PHY_QSERDES_TXA_PERL_LENGTH1 0x024C
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#define USB3PHY_QSERDES_TXA_PERL_LENGTH2 0x0250
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#define USB3PHY_QSERDES_TXA_SERDES_BYP_EN_OUT 0x0254
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#define USB3PHY_QSERDES_TXA_DEBUG_BUS_SEL 0x0258
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#define USB3PHY_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x025C
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#define USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x0260
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#define USB3PHY_QSERDES_TXA_TX_POL_INV 0x0264
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#define USB3PHY_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x0268
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN1 0x026C
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN2 0x0270
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN3 0x0274
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN4 0x0278
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN5 0x027C
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN6 0x0280
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN7 0x0284
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#define USB3PHY_QSERDES_TXA_BIST_PATTERN8 0x0288
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#define USB3PHY_QSERDES_TXA_LANE_MODE_1 0x028C
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#define USB3PHY_QSERDES_TXA_LANE_MODE_2 0x0290
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#define USB3PHY_QSERDES_TXA_LANE_MODE_3 0x0294
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#define USB3PHY_QSERDES_TXA_ATB_SEL1 0x0298
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#define USB3PHY_QSERDES_TXA_ATB_SEL2 0x029C
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#define USB3PHY_QSERDES_TXA_RCV_DETECT_LVL 0x02A0
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#define USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x02A4
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#define USB3PHY_QSERDES_TXA_PRBS_SEED1 0x02A8
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#define USB3PHY_QSERDES_TXA_PRBS_SEED2 0x02AC
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#define USB3PHY_QSERDES_TXA_PRBS_SEED3 0x02B0
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#define USB3PHY_QSERDES_TXA_PRBS_SEED4 0x02B4
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#define USB3PHY_QSERDES_TXA_RESET_GEN 0x02B8
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#define USB3PHY_QSERDES_TXA_RESET_GEN_MUXES 0x02BC
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#define USB3PHY_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x02C0
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#define USB3PHY_QSERDES_TXA_TX_INTERFACE_MODE 0x02C4
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#define USB3PHY_QSERDES_TXA_PWM_CTRL 0x02C8
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#define USB3PHY_QSERDES_TXA_PWM_ENCODED_OR_DATA 0x02CC
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND2 0x02D0
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND2 0x02D4
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND2 0x02D8
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND2 0x02DC
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND0_1 0x02E0
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND0_1 0x02E4
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND0_1 0x02E8
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#define USB3PHY_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND0_1 0x02EC
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#define USB3PHY_QSERDES_TXA_VMODE_CTRL1 0x02F0
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#define USB3PHY_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x02F4
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#define USB3PHY_QSERDES_TXA_BIST_STATUS 0x02F8
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#define USB3PHY_QSERDES_TXA_BIST_ERROR_COUNT1 0x02FC
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#define USB3PHY_QSERDES_TXA_BIST_ERROR_COUNT2 0x0300
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#define USB3PHY_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x0304
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#define USB3PHY_QSERDES_TXA_DIG_BKUP_CTRL 0x0308
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#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x0400
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#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x0404
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#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0408
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#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x040C
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#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x0410
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#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x0414
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x0418
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x041C
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x0420
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x0424
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x0428
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#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x042C
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#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0430
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#define USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x0434
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#define USB3PHY_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x0438
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#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x043C
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#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0440
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#define USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x0444
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#define USB3PHY_QSERDES_RXA_UCDR_SB2_THRESH1 0x0448
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#define USB3PHY_QSERDES_RXA_UCDR_SB2_THRESH2 0x044C
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#define USB3PHY_QSERDES_RXA_UCDR_SB2_GAIN1 0x0450
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#define USB3PHY_QSERDES_RXA_UCDR_SB2_GAIN2 0x0454
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#define USB3PHY_QSERDES_RXA_AUX_CONTROL 0x0458
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#define USB3PHY_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x045C
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#define USB3PHY_QSERDES_RXA_RCLK_AUXDATA_SEL 0x0460
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#define USB3PHY_QSERDES_RXA_AC_JTAG_ENABLE 0x0464
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#define USB3PHY_QSERDES_RXA_AC_JTAG_INITP 0x0468
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#define USB3PHY_QSERDES_RXA_AC_JTAG_INITN 0x046C
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#define USB3PHY_QSERDES_RXA_AC_JTAG_LVL 0x0470
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#define USB3PHY_QSERDES_RXA_AC_JTAG_MODE 0x0474
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#define USB3PHY_QSERDES_RXA_AC_JTAG_RESET 0x0478
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#define USB3PHY_QSERDES_RXA_RX_TERM_BW 0x047C
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#define USB3PHY_QSERDES_RXA_RX_RCVR_IQ_EN 0x0480
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#define USB3PHY_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x0484
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#define USB3PHY_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x0488
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#define USB3PHY_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x048C
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#define USB3PHY_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x0490
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#define USB3PHY_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x0494
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#define USB3PHY_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x0498
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#define USB3PHY_QSERDES_RXA_RX_IDAC_EN 0x049C
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#define USB3PHY_QSERDES_RXA_RX_IDAC_ENABLES 0x04A0
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#define USB3PHY_QSERDES_RXA_RX_IDAC_SIGN 0x04A4
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#define USB3PHY_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x04A8
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#define USB3PHY_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x04AC
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#define USB3PHY_QSERDES_RXA_DFE_1 0x04B0
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#define USB3PHY_QSERDES_RXA_DFE_2 0x04B4
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#define USB3PHY_QSERDES_RXA_DFE_3 0x04B8
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#define USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL1 0x04BC
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#define USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x04C0
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#define USB3PHY_QSERDES_RXA_GM_CAL 0x04C4
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#define USB3PHY_QSERDES_RXA_RX_EQ_GAIN2_LSB 0x04C8
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#define USB3PHY_QSERDES_RXA_RX_EQ_GAIN2_MSB 0x04CC
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#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x04D0
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#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x04D4
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#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x04D8
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#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x04DC
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#define USB3PHY_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x04E0
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#define USB3PHY_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x04E4
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#define USB3PHY_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x04E8
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#define USB3PHY_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x04EC
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#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x04F0
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#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x04F4
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#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x04F8
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#define USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x04FC
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#define USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x0500
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#define USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x0504
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#define USB3PHY_QSERDES_RXA_SIGDET_LVL 0x0508
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#define USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x050C
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#define USB3PHY_QSERDES_RXA_RX_BAND 0x0510
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#define USB3PHY_QSERDES_RXA_CDR_FREEZE_UP_DN 0x0514
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#define USB3PHY_QSERDES_RXA_CDR_RESET_OVERRIDE 0x0518
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#define USB3PHY_QSERDES_RXA_RX_INTERFACE_MODE 0x051C
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#define USB3PHY_QSERDES_RXA_JITTER_GEN_MODE 0x0520
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#define USB3PHY_QSERDES_RXA_BUJ_AMP 0x0524
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#define USB3PHY_QSERDES_RXA_SJ_AMP1 0x0528
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#define USB3PHY_QSERDES_RXA_SJ_AMP2 0x052C
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#define USB3PHY_QSERDES_RXA_SJ_PER1 0x0530
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#define USB3PHY_QSERDES_RXA_SJ_PER2 0x0534
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#define USB3PHY_QSERDES_RXA_BUJ_STEP_FREQ1 0x0538
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#define USB3PHY_QSERDES_RXA_BUJ_STEP_FREQ2 0x053C
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#define USB3PHY_QSERDES_RXA_PPM_OFFSET1 0x0540
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#define USB3PHY_QSERDES_RXA_PPM_OFFSET2 0x0544
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#define USB3PHY_QSERDES_RXA_SIGN_PPM_PERIOD1 0x0548
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#define USB3PHY_QSERDES_RXA_SIGN_PPM_PERIOD2 0x054C
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#define USB3PHY_QSERDES_RXA_RX_PWM_ENABLE_AND_DATA 0x0550
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#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0554
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#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0558
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#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR3_TIMEOUT_COUNT 0x055C
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#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR4_TIMEOUT_COUNT 0x0560
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#define USB3PHY_QSERDES_RXA_RX_MODE_00 0x0564
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#define USB3PHY_QSERDES_RXA_RX_MODE_01 0x0568
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#define USB3PHY_QSERDES_RXA_RX_MODE_10 0x056C
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#define USB3PHY_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x0570
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#define USB3PHY_QSERDES_RXA_PI_CTRL1 0x0574
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#define USB3PHY_QSERDES_RXA_PI_CTRL2 0x0578
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#define USB3PHY_QSERDES_RXA_PI_QUAD 0x057C
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#define USB3PHY_QSERDES_RXA_IDATA1 0x0580
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#define USB3PHY_QSERDES_RXA_IDATA2 0x0584
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#define USB3PHY_QSERDES_RXA_AUX_DATA1 0x0588
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#define USB3PHY_QSERDES_RXA_AUX_DATA2 0x058C
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#define USB3PHY_QSERDES_RXA_AC_JTAG_OUTP 0x0590
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#define USB3PHY_QSERDES_RXA_AC_JTAG_OUTN 0x0594
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#define USB3PHY_QSERDES_RXA_RX_SIGDET 0x0598
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_I 0x059C
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_IBAR 0x05A0
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_Q 0x05A4
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_QBAR 0x05A8
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_A 0x05AC
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_ABAR 0x05B0
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_SM_ON 0x05B4
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_CAL_DONE 0x05B8
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#define USB3PHY_QSERDES_RXA_IDAC_STATUS_SIGNERROR 0x05BC
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#define USB3PHY_QSERDES_RXA_READ_EQCODE 0x05C0
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#define USB3PHY_QSERDES_RXA_READ_OFFSETCODE 0x05C4
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#define USB3PHY_QSERDES_RXA_IA_ERROR_COUNTER_LOW 0x05C8
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#define USB3PHY_QSERDES_RXA_IA_ERROR_COUNTER_HIGH 0x05CC
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#define USB3PHY_QSERDES_RXA_VGA_READ_CODE 0x05D0
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#define USB3PHY_QSERDES_RXA_DFE_TAP1_READ_CODE 0x05D4
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#define USB3PHY_QSERDES_RXA_DFE_TAP2_READ_CODE 0x05D8
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#define USB3PHY_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x05DC
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#define USB3PHY_QSERDES_TXB_BIST_MODE_LANENO 0x0600
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#define USB3PHY_QSERDES_TXB_BIST_INVERT 0x0604
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#define USB3PHY_QSERDES_TXB_CLKBUF_ENABLE 0x0608
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#define USB3PHY_QSERDES_TXB_TX_EMP_POST1_LVL 0x060C
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#define USB3PHY_QSERDES_TXB_TX_POST2_EMPH 0x0610
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#define USB3PHY_QSERDES_TXB_TX_BOOST_LVL_UP_DN 0x0614
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#define USB3PHY_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x0618
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#define USB3PHY_QSERDES_TXB_TX_DRV_LVL 0x061C
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#define USB3PHY_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x0620
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#define USB3PHY_QSERDES_TXB_RESET_TSYNC_EN 0x0624
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#define USB3PHY_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x0628
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#define USB3PHY_QSERDES_TXB_TX_BAND 0x062C
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#define USB3PHY_QSERDES_TXB_SLEW_CNTL 0x0630
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#define USB3PHY_QSERDES_TXB_INTERFACE_SELECT 0x0634
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#define USB3PHY_QSERDES_TXB_LPB_EN 0x0638
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#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_TX 0x063C
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#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_RX 0x0640
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#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x0644
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#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0648
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#define USB3PHY_QSERDES_TXB_PERL_LENGTH1 0x064C
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#define USB3PHY_QSERDES_TXB_PERL_LENGTH2 0x0650
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#define USB3PHY_QSERDES_TXB_SERDES_BYP_EN_OUT 0x0654
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#define USB3PHY_QSERDES_TXB_DEBUG_BUS_SEL 0x0658
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#define USB3PHY_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x065C
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#define USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x0660
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#define USB3PHY_QSERDES_TXB_TX_POL_INV 0x0664
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#define USB3PHY_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x0668
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN1 0x066C
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN2 0x0670
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN3 0x0674
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN4 0x0678
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN5 0x067C
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN6 0x0680
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN7 0x0684
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#define USB3PHY_QSERDES_TXB_BIST_PATTERN8 0x0688
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#define USB3PHY_QSERDES_TXB_LANE_MODE_1 0x068C
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#define USB3PHY_QSERDES_TXB_LANE_MODE_2 0x0690
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#define USB3PHY_QSERDES_TXB_LANE_MODE_3 0x0694
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#define USB3PHY_QSERDES_TXB_ATB_SEL1 0x0698
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#define USB3PHY_QSERDES_TXB_ATB_SEL2 0x069C
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#define USB3PHY_QSERDES_TXB_RCV_DETECT_LVL 0x06A0
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#define USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x06A4
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#define USB3PHY_QSERDES_TXB_PRBS_SEED1 0x06A8
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#define USB3PHY_QSERDES_TXB_PRBS_SEED2 0x06AC
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#define USB3PHY_QSERDES_TXB_PRBS_SEED3 0x06B0
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#define USB3PHY_QSERDES_TXB_PRBS_SEED4 0x06B4
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#define USB3PHY_QSERDES_TXB_RESET_GEN 0x06B8
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#define USB3PHY_QSERDES_TXB_RESET_GEN_MUXES 0x06BC
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#define USB3PHY_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x06C0
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#define USB3PHY_QSERDES_TXB_TX_INTERFACE_MODE 0x06C4
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#define USB3PHY_QSERDES_TXB_PWM_CTRL 0x06C8
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#define USB3PHY_QSERDES_TXB_PWM_ENCODED_OR_DATA 0x06CC
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND2 0x06D0
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND2 0x06D4
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND2 0x06D8
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND2 0x06DC
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND0_1 0x06E0
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND0_1 0x06E4
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND0_1 0x06E8
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#define USB3PHY_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND0_1 0x06EC
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#define USB3PHY_QSERDES_TXB_VMODE_CTRL1 0x06F0
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#define USB3PHY_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x06F4
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#define USB3PHY_QSERDES_TXB_BIST_STATUS 0x06F8
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#define USB3PHY_QSERDES_TXB_BIST_ERROR_COUNT1 0x06FC
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#define USB3PHY_QSERDES_TXB_BIST_ERROR_COUNT2 0x0700
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#define USB3PHY_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x0704
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#define USB3PHY_QSERDES_TXB_DIG_BKUP_CTRL 0x0708
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#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x0800
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#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x0804
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#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0808
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#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x080C
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#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x0810
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#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x0814
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x0818
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x081C
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x0820
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x0824
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x0828
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#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x082C
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#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0830
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#define USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x0834
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#define USB3PHY_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x0838
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#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x083C
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#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0840
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#define USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x0844
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#define USB3PHY_QSERDES_RXB_UCDR_SB2_THRESH1 0x0848
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#define USB3PHY_QSERDES_RXB_UCDR_SB2_THRESH2 0x084C
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#define USB3PHY_QSERDES_RXB_UCDR_SB2_GAIN1 0x0850
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#define USB3PHY_QSERDES_RXB_UCDR_SB2_GAIN2 0x0854
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#define USB3PHY_QSERDES_RXB_AUX_CONTROL 0x0858
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#define USB3PHY_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x085C
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#define USB3PHY_QSERDES_RXB_RCLK_AUXDATA_SEL 0x0860
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#define USB3PHY_QSERDES_RXB_AC_JTAG_ENABLE 0x0864
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#define USB3PHY_QSERDES_RXB_AC_JTAG_INITP 0x0868
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#define USB3PHY_QSERDES_RXB_AC_JTAG_INITN 0x086C
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#define USB3PHY_QSERDES_RXB_AC_JTAG_LVL 0x0870
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#define USB3PHY_QSERDES_RXB_AC_JTAG_MODE 0x0874
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#define USB3PHY_QSERDES_RXB_AC_JTAG_RESET 0x0878
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#define USB3PHY_QSERDES_RXB_RX_TERM_BW 0x087C
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#define USB3PHY_QSERDES_RXB_RX_RCVR_IQ_EN 0x0880
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#define USB3PHY_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x0884
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#define USB3PHY_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x0888
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#define USB3PHY_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x088C
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#define USB3PHY_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x0890
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#define USB3PHY_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x0894
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#define USB3PHY_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x0898
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#define USB3PHY_QSERDES_RXB_RX_IDAC_EN 0x089C
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#define USB3PHY_QSERDES_RXB_RX_IDAC_ENABLES 0x08A0
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#define USB3PHY_QSERDES_RXB_RX_IDAC_SIGN 0x08A4
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#define USB3PHY_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x08A8
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#define USB3PHY_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x08AC
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#define USB3PHY_QSERDES_RXB_DFE_1 0x08B0
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#define USB3PHY_QSERDES_RXB_DFE_2 0x08B4
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#define USB3PHY_QSERDES_RXB_DFE_3 0x08B8
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#define USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL1 0x08BC
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#define USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x08C0
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#define USB3PHY_QSERDES_RXB_GM_CAL 0x08C4
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#define USB3PHY_QSERDES_RXB_RX_EQ_GAIN2_LSB 0x08C8
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#define USB3PHY_QSERDES_RXB_RX_EQ_GAIN2_MSB 0x08CC
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#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x08D0
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#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x08D4
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#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x08D8
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#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x08DC
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#define USB3PHY_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x08E0
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#define USB3PHY_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x08E4
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#define USB3PHY_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x08E8
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#define USB3PHY_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x08EC
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#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x08F0
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#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x08F4
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#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x08F8
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#define USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x08FC
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#define USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x0900
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#define USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x0904
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#define USB3PHY_QSERDES_RXB_SIGDET_LVL 0x0908
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#define USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x090C
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#define USB3PHY_QSERDES_RXB_RX_BAND 0x0910
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#define USB3PHY_QSERDES_RXB_CDR_FREEZE_UP_DN 0x0914
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#define USB3PHY_QSERDES_RXB_CDR_RESET_OVERRIDE 0x0918
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#define USB3PHY_QSERDES_RXB_RX_INTERFACE_MODE 0x091C
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#define USB3PHY_QSERDES_RXB_JITTER_GEN_MODE 0x0920
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#define USB3PHY_QSERDES_RXB_BUJ_AMP 0x0924
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#define USB3PHY_QSERDES_RXB_SJ_AMP1 0x0928
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#define USB3PHY_QSERDES_RXB_SJ_AMP2 0x092C
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#define USB3PHY_QSERDES_RXB_SJ_PER1 0x0930
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#define USB3PHY_QSERDES_RXB_SJ_PER2 0x0934
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#define USB3PHY_QSERDES_RXB_BUJ_STEP_FREQ1 0x0938
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#define USB3PHY_QSERDES_RXB_BUJ_STEP_FREQ2 0x093C
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#define USB3PHY_QSERDES_RXB_PPM_OFFSET1 0x0940
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#define USB3PHY_QSERDES_RXB_PPM_OFFSET2 0x0944
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#define USB3PHY_QSERDES_RXB_SIGN_PPM_PERIOD1 0x0948
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#define USB3PHY_QSERDES_RXB_SIGN_PPM_PERIOD2 0x094C
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#define USB3PHY_QSERDES_RXB_RX_PWM_ENABLE_AND_DATA 0x0950
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#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0954
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#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0958
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#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR3_TIMEOUT_COUNT 0x095C
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#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR4_TIMEOUT_COUNT 0x0960
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#define USB3PHY_QSERDES_RXB_RX_MODE_00 0x0964
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#define USB3PHY_QSERDES_RXB_RX_MODE_01 0x0968
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#define USB3PHY_QSERDES_RXB_RX_MODE_10 0x096C
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#define USB3PHY_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x0970
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#define USB3PHY_QSERDES_RXB_PI_CTRL1 0x0974
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#define USB3PHY_QSERDES_RXB_PI_CTRL2 0x0978
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#define USB3PHY_QSERDES_RXB_PI_QUAD 0x097C
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#define USB3PHY_QSERDES_RXB_IDATA1 0x0980
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#define USB3PHY_QSERDES_RXB_IDATA2 0x0984
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#define USB3PHY_QSERDES_RXB_AUX_DATA1 0x0988
|
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#define USB3PHY_QSERDES_RXB_AUX_DATA2 0x098C
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#define USB3PHY_QSERDES_RXB_AC_JTAG_OUTP 0x0990
|
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#define USB3PHY_QSERDES_RXB_AC_JTAG_OUTN 0x0994
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#define USB3PHY_QSERDES_RXB_RX_SIGDET 0x0998
|
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_I 0x099C
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_IBAR 0x09A0
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_Q 0x09A4
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_QBAR 0x09A8
|
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_A 0x09AC
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_ABAR 0x09B0
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_SM_ON 0x09B4
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_CAL_DONE 0x09B8
|
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#define USB3PHY_QSERDES_RXB_IDAC_STATUS_SIGNERROR 0x09BC
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#define USB3PHY_QSERDES_RXB_READ_EQCODE 0x09C0
|
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#define USB3PHY_QSERDES_RXB_READ_OFFSETCODE 0x09C4
|
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#define USB3PHY_QSERDES_RXB_IA_ERROR_COUNTER_LOW 0x09C8
|
|
#define USB3PHY_QSERDES_RXB_IA_ERROR_COUNTER_HIGH 0x09CC
|
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#define USB3PHY_QSERDES_RXB_VGA_READ_CODE 0x09D0
|
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#define USB3PHY_QSERDES_RXB_DFE_TAP1_READ_CODE 0x09D4
|
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#define USB3PHY_QSERDES_RXB_DFE_TAP2_READ_CODE 0x09D8
|
|
#define USB3PHY_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x09DC
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#define USB3PHY_PCS_MISC_TYPEC_CTRL 0x0A00
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#define USB3PHY_PCS_MISC_TYPEC_STATUS 0x0A04
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#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE0_INDEX 0x0A08
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#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE1_INDEX 0x0A0C
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#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE2_INDEX 0x0A10
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#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE3_INDEX 0x0A14
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#define USB3PHY_PCS_MISC_PLACEHOLDER_STATUS 0x0A18
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#define USB3PHY_PCS_MISC_DEBUG_BUS_0_STATUS 0x0A1C
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#define USB3PHY_PCS_MISC_DEBUG_BUS_1_STATUS 0x0A20
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#define USB3PHY_PCS_MISC_DEBUG_BUS_2_STATUS 0x0A24
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#define USB3PHY_PCS_MISC_DEBUG_BUS_3_STATUS 0x0A28
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#define USB3PHY_PCS_MISC_BIST_CTRL 0x0A2C
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#define USB3PHY_PCS_SW_RESET 0x0C00
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#define USB3PHY_PCS_POWER_DOWN_CONTROL 0x0C04
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#define USB3PHY_PCS_START_CONTROL 0x0C08
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#define USB3PHY_PCS_TXMGN_V0 0x0C0C
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#define USB3PHY_PCS_TXMGN_V1 0x0C10
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#define USB3PHY_PCS_TXMGN_V2 0x0C14
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#define USB3PHY_PCS_TXMGN_V3 0x0C18
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#define USB3PHY_PCS_TXMGN_V4 0x0C1C
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#define USB3PHY_PCS_TXMGN_LS 0x0C20
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#define USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x0C24
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0C28
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#define USB3PHY_PCS_TXDEEMPH_M6DB_V1 0x0C2C
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V1 0x0C30
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#define USB3PHY_PCS_TXDEEMPH_M6DB_V2 0x0C34
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V2 0x0C38
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#define USB3PHY_PCS_TXDEEMPH_M6DB_V3 0x0C3C
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V3 0x0C40
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#define USB3PHY_PCS_TXDEEMPH_M6DB_V4 0x0C44
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V4 0x0C48
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#define USB3PHY_PCS_TXDEEMPH_M6DB_LS 0x0C4C
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#define USB3PHY_PCS_TXDEEMPH_M3P5DB_LS 0x0C50
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#define USB3PHY_PCS_ENDPOINT_REFCLK_DRIVE 0x0C54
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#define USB3PHY_PCS_RX_IDLE_DTCT_CNTRL 0x0C58
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#define USB3PHY_PCS_RATE_SLEW_CNTRL 0x0C5C
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#define USB3PHY_PCS_POWER_STATE_CONFIG1 0x0C60
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#define USB3PHY_PCS_POWER_STATE_CONFIG2 0x0C64
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#define USB3PHY_PCS_POWER_STATE_CONFIG3 0x0C68
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#define USB3PHY_PCS_POWER_STATE_CONFIG4 0x0C6C
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#define USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0x0C70
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#define USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x0C74
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#define USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x0C78
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#define USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x0C7C
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#define USB3PHY_PCS_LOCK_DETECT_CONFIG1 0x0C80
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#define USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x0C84
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#define USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x0C88
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#define USB3PHY_PCS_TSYNC_RSYNC_TIME 0x0C8C
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#define USB3PHY_PCS_SIGDET_LOW_2_IDLE_TIME 0x0C90
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#define USB3PHY_PCS_BEACON_2_IDLE_TIME_L 0x0C94
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#define USB3PHY_PCS_BEACON_2_IDLE_TIME_H 0x0C98
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#define USB3PHY_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x0C9C
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#define USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0CA0
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#define USB3PHY_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0CA4
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#define USB3PHY_PCS_PLL_LOCK_CHK_DLY_TIME 0x0CA8
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#define USB3PHY_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0CAC
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#define USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0CB0
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#define USB3PHY_PCS_LFPS_TX_END_CNT_P2U3_START 0x0CB4
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#define USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x0CB8
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#define USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x0CBC
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#define USB3PHY_PCS_TXONESZEROS_RUN_LENGTH 0x0CC0
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#define USB3PHY_PCS_FLL_CNTRL1 0x0CC4
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#define USB3PHY_PCS_FLL_CNTRL2 0x0CC8
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#define USB3PHY_PCS_FLL_CNT_VAL_L 0x0CCC
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#define USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0x0CD0
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#define USB3PHY_PCS_FLL_MAN_CODE 0x0CD4
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#define USB3PHY_PCS_AUTONOMOUS_MODE_CTRL 0x0CD8
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#define USB3PHY_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0CDC
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#define USB3PHY_PCS_ARCVR_DTCT_EN_PERIOD 0x0CE0
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#define USB3PHY_PCS_ARCVR_DTCT_CM_DLY 0x0CE4
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#define USB3PHY_PCS_ALFPS_DEGLITCH_VAL 0x0CE8
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#define USB3PHY_PCS_INSIG_SW_CTRL1 0x0CEC
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#define USB3PHY_PCS_INSIG_SW_CTRL2 0x0CF0
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#define USB3PHY_PCS_INSIG_SW_CTRL3 0x0CF4
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#define USB3PHY_PCS_INSIG_MX_CTRL1 0x0CF8
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#define USB3PHY_PCS_INSIG_MX_CTRL2 0x0CFC
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#define USB3PHY_PCS_INSIG_MX_CTRL3 0x0D00
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#define USB3PHY_PCS_OUTSIG_SW_CTRL1 0x0D04
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#define USB3PHY_PCS_OUTSIG_MX_CTRL1 0x0D08
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#define USB3PHY_PCS_CLK_DEBUG_BYPASS_CTRL 0x0D0C
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#define USB3PHY_PCS_TEST_CONTROL 0x0D10
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#define USB3PHY_PCS_TEST_CONTROL2 0x0D14
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#define USB3PHY_PCS_TEST_CONTROL3 0x0D18
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#define USB3PHY_PCS_TEST_CONTROL4 0x0D1C
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#define USB3PHY_PCS_TEST_CONTROL5 0x0D20
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#define USB3PHY_PCS_TEST_CONTROL6 0x0D24
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#define USB3PHY_PCS_TEST_CONTROL7 0x0D28
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#define USB3PHY_PCS_COM_RESET_CONTROL 0x0D2C
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#define USB3PHY_PCS_BIST_CTRL 0x0D30
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#define USB3PHY_PCS_PRBS_POLY0 0x0D34
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#define USB3PHY_PCS_PRBS_POLY1 0x0D38
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#define USB3PHY_PCS_PRBS_SEED0 0x0D3C
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#define USB3PHY_PCS_PRBS_SEED1 0x0D40
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#define USB3PHY_PCS_FIXED_PAT_CTRL 0x0D44
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#define USB3PHY_PCS_FIXED_PAT0 0x0D48
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#define USB3PHY_PCS_FIXED_PAT1 0x0D4C
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#define USB3PHY_PCS_FIXED_PAT2 0x0D50
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#define USB3PHY_PCS_FIXED_PAT3 0x0D54
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#define USB3PHY_PCS_COM_CLK_SWITCH_CTRL 0x0D58
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#define USB3PHY_PCS_ELECIDLE_DLY_SEL 0x0D5C
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#define USB3PHY_PCS_SPARE1 0x0D60
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#define USB3PHY_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x0D64
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#define USB3PHY_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x0D68
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#define USB3PHY_PCS_BIST_CHK_STATUS 0x0D6C
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#define USB3PHY_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x0D70
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#define USB3PHY_PCS_PCS_STATUS 0x0D74
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#define USB3PHY_PCS_PCS_STATUS2 0x0D78
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#define USB3PHY_PCS_PCS_STATUS3 0x0D7C
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#define USB3PHY_PCS_COM_RESET_STATUS 0x0D80
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#define USB3PHY_PCS_OSC_DTCT_STATUS 0x0D84
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#define USB3PHY_PCS_REVISION_ID0 0x0D88
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#define USB3PHY_PCS_REVISION_ID1 0x0D8C
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#define USB3PHY_PCS_REVISION_ID2 0x0D90
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#define USB3PHY_PCS_REVISION_ID3 0x0D94
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#define USB3PHY_PCS_DEBUG_BUS_0_STATUS 0x0D98
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#define USB3PHY_PCS_DEBUG_BUS_1_STATUS 0x0D9C
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#define USB3PHY_PCS_DEBUG_BUS_2_STATUS 0x0DA0
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#define USB3PHY_PCS_DEBUG_BUS_3_STATUS 0x0DA4
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#define USB3PHY_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x0DA8
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#define USB3PHY_PCS_OSC_DTCT_ACTIONS 0x0DAC
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#define USB3PHY_PCS_SIGDET_CNTRL 0x0DB0
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#define USB3PHY_PCS_IDAC_CAL_CNTRL 0x0DB4
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#define USB3PHY_PCS_CMN_ACK_OUT_SEL 0x0DB8
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#define USB3PHY_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x0DBC
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#define USB3PHY_PCS_AUTONOMOUS_MODE_STATUS 0x0DC0
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#define USB3PHY_PCS_ENDPOINT_REFCLK_CNTRL 0x0DC4
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#define USB3PHY_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x0DC8
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#define USB3PHY_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x0DCC
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#define USB3PHY_PCS_EPCLK_DLY_COUNT_VAL_L 0x0DD0
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#define USB3PHY_PCS_EPCLK_DLY_COUNT_VAL_H 0x0DD4
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#define USB3PHY_PCS_RX_SIGDET_LVL 0x0DD8
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#define USB3PHY_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x0DDC
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#define USB3PHY_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x0DE0
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#define USB3PHY_PCS_AUTONOMOUS_MODE_CTRL2 0x0DE4
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#define USB3PHY_PCS_RXTERMINATION_DLY_SEL 0x0DE8
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#define USB3PHY_PCS_LFPS_PER_TIMER_VAL 0x0DEC
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#define USB3PHY_PCS_SIGDET_STARTUP_TIMER_VAL 0x0DF0
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#define USB3PHY_PCS_LOCK_DETECT_CONFIG4 0x0DF4
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#define USB3PHY_PCS_RX_SIGDET_DTCT_CNTRL 0x0DF8
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#define USB3PHY_PCS_PCS_STATUS4 0x0DFC
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#define USB3PHY_PCS_PCS_STATUS4_CLEAR 0x0E00
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#define USB3PHY_PCS_DEC_ERROR_COUNT_STATUS 0x0E04
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#define USB3PHY_PCS_COMMA_POS_STATUS 0x0E08
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#define USB3PHY_PCS_REFGEN_REQ_CONFIG1 0x0E0C
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#define USB3PHY_PCS_REFGEN_REQ_CONFIG2 0x0E10
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#define USB3PHY_PCS_REFGEN_REQ_CONFIG3 0x0E14
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#endif /* _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H */
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