0f2ca9fb63
Add DT files for global clock controller, multimedia clock
controller and peripheral gpu clock drivers to support gpu
PLLs and RCGs.
This snapshot of the gcc-sdm660, gpu-sdm660
and mmcc-sdm660 DT as of msm-4.14 'commit
4d7da9f5ed3ac19c8 (" Merge "defconfig: sa8195: Enable
config for dyn splash"")'.
Change-Id: I7f32a5cfc037d7d91738d5b36aad2f97964bf2c4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
212 lines
6.5 KiB
C
212 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H
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#define _DT_BINDINGS_CLK_MSM_MMCC_660_H
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#define MMSS_CAMSS_JPEG0_VOTE_CLK 0
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#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1
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#define AHB_CLK_SRC 5
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#define BYTE0_CLK_SRC 6
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#define BYTE1_CLK_SRC 7
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#define CAMSS_GP0_CLK_SRC 8
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#define CAMSS_GP1_CLK_SRC 9
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#define CCI_CLK_SRC 10
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#define CPP_CLK_SRC 11
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#define CSI0_CLK_SRC 12
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#define CSI0PHYTIMER_CLK_SRC 13
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#define CSI1_CLK_SRC 14
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#define CSI1PHYTIMER_CLK_SRC 15
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#define CSI2_CLK_SRC 16
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#define CSI2PHYTIMER_CLK_SRC 17
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#define CSI3_CLK_SRC 18
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#define CSIPHY_CLK_SRC 19
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#define DP_AUX_CLK_SRC 20
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#define DP_CRYPTO_CLK_SRC 21
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#define DP_GTC_CLK_SRC 22
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#define DP_LINK_CLK_SRC 23
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#define DP_PIXEL_CLK_SRC 24
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#define ESC0_CLK_SRC 25
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#define ESC1_CLK_SRC 26
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#define JPEG0_CLK_SRC 27
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#define MCLK0_CLK_SRC 28
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#define MCLK1_CLK_SRC 29
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#define MCLK2_CLK_SRC 30
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#define MCLK3_CLK_SRC 31
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#define MDP_CLK_SRC 32
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#define MMPLL0_PLL 33
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#define MMPLL0_PLL_OUT_AUX 34
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#define MMPLL0_PLL_OUT_AUX2 35
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#define MMPLL0_PLL_OUT_EARLY 36
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#define MMPLL0_PLL_OUT_MAIN 37
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#define MMPLL0_PLL_OUT_TEST 38
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#define MMPLL10_PLL 39
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#define MMPLL10_PLL_OUT_AUX 40
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#define MMPLL10_PLL_OUT_AUX2 41
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#define MMPLL10_PLL_OUT_EARLY 42
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#define MMPLL10_PLL_OUT_MAIN 43
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#define MMPLL10_PLL_OUT_TEST 44
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#define MMPLL1_PLL 45
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#define MMPLL1_PLL_OUT_AUX 46
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#define MMPLL1_PLL_OUT_AUX2 47
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#define MMPLL1_PLL_OUT_EARLY 48
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#define MMPLL1_PLL_OUT_MAIN 49
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#define MMPLL1_PLL_OUT_TEST 50
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#define MMPLL3_PLL 51
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#define MMPLL3_PLL_OUT_AUX 52
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#define MMPLL3_PLL_OUT_AUX2 53
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#define MMPLL3_PLL_OUT_EARLY 54
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#define MMPLL3_PLL_OUT_MAIN 55
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#define MMPLL3_PLL_OUT_TEST 56
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#define MMPLL4_PLL 57
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#define MMPLL4_PLL_OUT_AUX 58
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#define MMPLL4_PLL_OUT_AUX2 59
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#define MMPLL4_PLL_OUT_EARLY 60
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#define MMPLL4_PLL_OUT_MAIN 61
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#define MMPLL4_PLL_OUT_TEST 62
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#define MMPLL5_PLL 63
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#define MMPLL5_PLL_OUT_AUX 64
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#define MMPLL5_PLL_OUT_AUX2 65
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#define MMPLL5_PLL_OUT_EARLY 66
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#define MMPLL5_PLL_OUT_MAIN 67
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#define MMPLL5_PLL_OUT_TEST 68
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#define MMPLL6_PLL 69
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#define MMPLL6_PLL_OUT_AUX 70
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#define MMPLL6_PLL_OUT_AUX2 71
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#define MMPLL6_PLL_OUT_EARLY 72
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#define MMPLL6_PLL_OUT_MAIN 73
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#define MMPLL6_PLL_OUT_TEST 74
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#define MMPLL7_PLL 75
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#define MMPLL7_PLL_OUT_AUX 76
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#define MMPLL7_PLL_OUT_AUX2 77
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#define MMPLL7_PLL_OUT_EARLY 78
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#define MMPLL7_PLL_OUT_MAIN 79
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#define MMPLL7_PLL_OUT_TEST 80
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#define MMPLL8_PLL 81
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#define MMPLL8_PLL_OUT_AUX 82
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#define MMPLL8_PLL_OUT_AUX2 83
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#define MMPLL8_PLL_OUT_EARLY 84
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#define MMPLL8_PLL_OUT_MAIN 85
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#define MMPLL8_PLL_OUT_TEST 86
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#define MMSS_BIMC_SMMU_AHB_CLK 87
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#define MMSS_BIMC_SMMU_AXI_CLK 88
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#define MMSS_CAMSS_AHB_CLK 89
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#define MMSS_CAMSS_CCI_AHB_CLK 90
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#define MMSS_CAMSS_CCI_CLK 91
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#define MMSS_CAMSS_CPHY_CSID0_CLK 92
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#define MMSS_CAMSS_CPHY_CSID1_CLK 93
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#define MMSS_CAMSS_CPHY_CSID2_CLK 94
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#define MMSS_CAMSS_CPHY_CSID3_CLK 95
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#define MMSS_CAMSS_CPP_AHB_CLK 96
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#define MMSS_CAMSS_CPP_AXI_CLK 97
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#define MMSS_CAMSS_CPP_CLK 98
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#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 99
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#define MMSS_CAMSS_CSI0_AHB_CLK 100
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#define MMSS_CAMSS_CSI0_CLK 101
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#define MMSS_CAMSS_CSI0PHYTIMER_CLK 102
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#define MMSS_CAMSS_CSI0PIX_CLK 103
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#define MMSS_CAMSS_CSI0RDI_CLK 104
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#define MMSS_CAMSS_CSI1_AHB_CLK 105
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#define MMSS_CAMSS_CSI1_CLK 106
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#define MMSS_CAMSS_CSI1PHYTIMER_CLK 107
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#define MMSS_CAMSS_CSI1PIX_CLK 108
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#define MMSS_CAMSS_CSI1RDI_CLK 109
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#define MMSS_CAMSS_CSI2_AHB_CLK 110
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#define MMSS_CAMSS_CSI2_CLK 111
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#define MMSS_CAMSS_CSI2PHYTIMER_CLK 112
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#define MMSS_CAMSS_CSI2PIX_CLK 113
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#define MMSS_CAMSS_CSI2RDI_CLK 114
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#define MMSS_CAMSS_CSI3_AHB_CLK 115
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#define MMSS_CAMSS_CSI3_CLK 116
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#define MMSS_CAMSS_CSI3PIX_CLK 117
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#define MMSS_CAMSS_CSI3RDI_CLK 118
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#define MMSS_CAMSS_CSI_VFE0_CLK 119
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#define MMSS_CAMSS_CSI_VFE1_CLK 120
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#define MMSS_CAMSS_CSIPHY0_CLK 121
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#define MMSS_CAMSS_CSIPHY1_CLK 122
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#define MMSS_CAMSS_CSIPHY2_CLK 123
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#define MMSS_CAMSS_GP0_CLK 124
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#define MMSS_CAMSS_GP1_CLK 125
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#define MMSS_CAMSS_ISPIF_AHB_CLK 126
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#define MMSS_CAMSS_JPEG0_CLK 127
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#define MMSS_CAMSS_JPEG_AHB_CLK 128
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#define MMSS_CAMSS_JPEG_AXI_CLK 129
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#define MMSS_CAMSS_MCLK0_CLK 130
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#define MMSS_CAMSS_MCLK1_CLK 131
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#define MMSS_CAMSS_MCLK2_CLK 132
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#define MMSS_CAMSS_MCLK3_CLK 133
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#define MMSS_CAMSS_MICRO_AHB_CLK 134
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#define MMSS_CAMSS_TOP_AHB_CLK 135
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#define MMSS_CAMSS_VFE0_AHB_CLK 136
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#define MMSS_CAMSS_VFE0_CLK 137
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#define MMSS_CAMSS_VFE0_STREAM_CLK 138
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#define MMSS_CAMSS_VFE1_AHB_CLK 139
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#define MMSS_CAMSS_VFE1_CLK 140
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#define MMSS_CAMSS_VFE1_STREAM_CLK 141
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#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 142
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#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 143
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#define MMSS_CSIPHY_AHB2CRIF_CLK 144
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#define MMSS_CXO_CLK 145
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#define MMSS_MDSS_AHB_CLK 146
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#define MMSS_MDSS_AXI_CLK 147
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#define MMSS_MDSS_BYTE0_CLK 148
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#define MMSS_MDSS_BYTE0_INTF_CLK 149
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#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 150
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#define MMSS_MDSS_BYTE1_CLK 151
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#define MMSS_MDSS_BYTE1_INTF_CLK 152
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#define MMSS_MDSS_DP_AUX_CLK 153
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#define MMSS_MDSS_DP_CRYPTO_CLK 154
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#define MMSS_MDSS_DP_GTC_CLK 155
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#define MMSS_MDSS_DP_LINK_CLK 156
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#define MMSS_MDSS_DP_LINK_INTF_CLK 157
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#define MMSS_MDSS_DP_PIXEL_CLK 158
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#define MMSS_MDSS_ESC0_CLK 159
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#define MMSS_MDSS_ESC1_CLK 160
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#define MMSS_MDSS_HDMI_DP_AHB_CLK 161
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#define MMSS_MDSS_MDP_CLK 162
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#define MMSS_MDSS_PCLK0_CLK 163
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#define MMSS_MDSS_PCLK1_CLK 164
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#define MMSS_MDSS_ROT_CLK 165
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#define MMSS_MDSS_VSYNC_CLK 166
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#define MMSS_MISC_AHB_CLK 167
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#define MMSS_MISC_CXO_CLK 168
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#define MMSS_MNOC_AHB_CLK 169
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#define MMSS_SNOC_DVM_AXI_CLK 170
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#define MMSS_THROTTLE_CAMSS_AHB_CLK 171
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#define MMSS_THROTTLE_CAMSS_AXI_CLK 172
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#define MMSS_THROTTLE_CAMSS_CXO_CLK 173
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#define MMSS_THROTTLE_MDSS_AHB_CLK 174
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#define MMSS_THROTTLE_MDSS_AXI_CLK 175
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#define MMSS_THROTTLE_MDSS_CXO_CLK 176
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#define MMSS_THROTTLE_VIDEO_AHB_CLK 177
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#define MMSS_THROTTLE_VIDEO_AXI_CLK 178
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#define MMSS_THROTTLE_VIDEO_CXO_CLK 179
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#define MMSS_VIDEO_AHB_CLK 180
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#define MMSS_VIDEO_AXI_CLK 181
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#define MMSS_VIDEO_CORE_CLK 182
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#define MMSS_VIDEO_SUBCORE0_CLK 183
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#define PCLK0_CLK_SRC 184
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#define PCLK1_CLK_SRC 185
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#define ROT_CLK_SRC 186
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#define VFE0_CLK_SRC 187
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#define VFE1_CLK_SRC 188
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#define VIDEO_CORE_CLK_SRC 189
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#define VSYNC_CLK_SRC 190
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#define MMSS_MDSS_BYTE1_INTF_DIV_CLK 191
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#define BIMC_SMMU_GDSC 0
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#define CAMSS_CPP_GDSC 1
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#define CAMSS_TOP_GDSC 2
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#define CAMSS_VFE0_GDSC 3
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#define CAMSS_VFE1_GDSC 4
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#define MDSS_GDSC 5
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#define VIDEO_SUBCORE0_GDSC 6
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#define VIDEO_TOP_GDSC 7
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#define CAMSS_MICRO_BCR 0
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#endif
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