4a976aa230
Add snapshot of mba based modem pil driver based on 4.14
to 4.19 kernel.
This is snapshot of the MBA base modem PIL driver as of
msm-4.14 'commit 78bed541dbf8950be ("Merge "msm:
camera: hyp: To fix Stack overflow"")'.
Change-Id: Ie4e2e5998ae379c0f49d64d3d4126c59786a42a9
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Chetan C R <cchinnad@codeaurora.org>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MSM_PIL_Q6V5_H
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#define __MSM_PIL_Q6V5_H
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#include "peripheral-loader.h"
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struct regulator;
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struct clk;
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struct pil_device;
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struct platform_device;
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struct q6v5_data {
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void __iomem *reg_base;
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void __iomem *rmb_base;
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void __iomem *cxrail_bhs; /* External BHS register */
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struct clk *xo; /* XO clock source */
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struct clk *pnoc_clk; /* PNOC bus clock source */
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struct clk *ahb_clk; /* PIL access to registers */
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struct clk *axi_clk; /* CPU access to memory */
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struct clk *core_clk; /* CPU core */
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struct clk *reg_clk; /* CPU access registers */
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struct clk *gpll0_mss_clk; /* GPLL0 to MSS connection */
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struct clk *rom_clk; /* Boot ROM */
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struct clk *snoc_axi_clk;
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struct clk *mnoc_axi_clk;
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struct clk *qdss_clk;
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struct clk *prng_clk;
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struct clk *axis2_clk;
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void __iomem *axi_halt_base; /* Halt base of q6, mss,
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* nc are in same 4K page
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*/
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void __iomem *axi_halt_q6;
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void __iomem *axi_halt_mss;
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void __iomem *axi_halt_nc;
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void __iomem *restart_reg;
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void __iomem *pdc_sync;
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void __iomem *alt_reset;
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struct regulator *vreg;
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struct regulator *vreg_cx;
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struct regulator *vreg_mx;
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struct regulator *vreg_pll;
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bool is_booted;
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struct pil_desc desc;
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bool self_auth;
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phys_addr_t mba_dp_phys;
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void *mba_dp_virt;
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size_t mba_dp_size;
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size_t dp_size;
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bool qdsp6v55;
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bool qdsp6v5_2_0;
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bool qdsp6v56;
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bool qdsp6v56_1_3;
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bool qdsp6v56_1_5;
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bool qdsp6v56_1_8;
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bool qdsp6v56_1_8_inrush_current;
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bool qdsp6v56_1_10;
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bool qdsp6v61_1_1;
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bool qdsp6v62_1_2;
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bool qdsp6v62_1_4;
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bool qdsp6v62_1_5;
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bool qdsp6v65_1_0;
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bool non_elf_image;
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bool restart_reg_sec;
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bool override_acc;
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int override_acc_1;
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int mss_pdc_offset;
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int smem_id;
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bool ahb_clk_vote;
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bool mx_spike_wa;
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bool reset_clk;
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};
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int pil_q6v5_make_proxy_votes(struct pil_desc *pil);
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void pil_q6v5_remove_proxy_votes(struct pil_desc *pil);
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void pil_q6v5_halt_axi_port(struct pil_desc *pil, void __iomem *halt_base);
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void pil_q6v5_shutdown(struct pil_desc *pil);
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int pil_q6v5_reset(struct pil_desc *pil);
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void assert_clamps(struct pil_desc *pil);
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struct q6v5_data *pil_q6v5_init(struct platform_device *pdev);
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#endif
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