2b8ff9f276
Currently many IRQ mapping functions and data structures use the __init and __initdata optimisations. These result in the relevant functions being innaccessible after boot time. However for deferred IRQ assignment it is important to have access to these functions at PCI device enable time. Therefore, remove the optimisation from the relevant data structures and functions to prepare for deferred IRQ assignment. Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/*
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* arch/sh/drivers/pci/fixups-rts7751r2d.c
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*
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* RTS7751R2D / LBOXRE2 PCI fixups
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*
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* Copyright (C) 2003 Lineo uSolutions, Inc.
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* Copyright (C) 2004 Paul Mundt
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include <mach/lboxre2.h>
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#include <mach/r2d.h>
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#include "pci-sh4.h"
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#include <generated/machtypes.h>
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#define PCIMCR_MRSET_OFF 0xBFFFFFFF
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#define PCIMCR_RFSH_OFF 0xFFFFFFFB
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static u8 rts7751r2d_irq_tab[] = {
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IRQ_PCI_INTA,
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IRQ_PCI_INTB,
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IRQ_PCI_INTC,
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IRQ_PCI_INTD,
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};
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static char lboxre2_irq_tab[] = {
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IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
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};
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int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
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{
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if (mach_is_lboxre2())
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return lboxre2_irq_tab[slot];
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else
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return rts7751r2d_irq_tab[slot];
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}
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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unsigned long bcr1, mcr;
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bcr1 = __raw_readl(SH7751_BCR1);
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bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
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pci_write_reg(chan, bcr1, SH4_PCIBCR1);
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/* Enable all interrupts, so we known what to fix */
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pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
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pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
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pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
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pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
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mcr = __raw_readl(SH7751_MCR);
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mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
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pci_write_reg(chan, mcr, SH4_PCIMCR);
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pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
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pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
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pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
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pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
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return 0;
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}
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