779b095234
* aosp/android-4.19-stable: Revert "USB: HCD: Fix URB giveback issue in tasklet function" drm/msm/mdp5: Fix global state lock backoff drm: bridge: sii8620: fix possible off-by-one drm/mediatek: dpi: Remove output format of YUV drm/rockchip: vop: Don't crash for invalid duplicate_state() drm/vc4: dsi: Correct DSI divider calculations media: hdpvr: fix error value returns in hdpvr_read drm: bridge: adv7511: Add check for mipi_dsi_driver_register wifi: iwlegacy: 4965: fix potential off-by-one overflow in il4965_rs_fill_link_cmd() ath9k: fix use-after-free in ath9k_hif_usb_rx_cb media: tw686x: Register the irq at the end of probe i2c: Fix a potential use after free drm/mediatek: Add pull-down MIPI operation in mtk_dsi_poweroff function drm/radeon: fix potential buffer overflow in ni_set_mc_special_registers() wifi: rtlwifi: fix error codes in rtl_debugfs_set_write_h2c() ath10k: do not enforce interrupt trigger type dm: return early from dm_pr_call() if DM device is suspended thermal/tools/tmon: Include pthread and time headers in tmon.h nohz/full, sched/rt: Fix missed tick-reenabling bug in dequeue_task_rt() regulator: of: Fix refcount leak bug in of_get_regulation_constraints() arm64: dts: qcom: msm8916: Fix typo in pronto remoteproc node bus: hisi_lpc: fix missing platform_device_put() in hisi_lpc_acpi_probe() ARM: dts: qcom: pm8841: add required thermal-sensor-cells cpufreq: zynq: Fix refcount leak in zynq_get_revision ARM: OMAP2+: Fix refcount leak in omap3xxx_prm_late_init soc: fsl: guts: machine variable might be unset ARM: dts: ast2500-evb: fix board compatible x86/pmem: Fix platform-device leak in error path ARM: bcm: Fix refcount leak in bcm_kona_smc_init meson-mx-socinfo: Fix refcount leak in meson_mx_socinfo_init ARM: findbit: fix overflowing offset selinux: Add boundary check in put_entry() PM: hibernate: defer device probing when resuming from hibernation arm64: dts: qcom: ipq8074: fix NAND node name ACPI: LPSS: Fix missing check in register_device_clock() ACPI: PM: save NVS memory for Lenovo G40-45 ACPI: EC: Remove duplicate ThinkPad X1 Carbon 6th entry from DMI quirks ARM: OMAP2+: display: Fix refcount leak bug ARM: dts: imx6ul: fix qspi node compatible ARM: dts: imx6ul: fix lcdif node compatible ARM: dts: imx6ul: change operating-points to uint32-matrix ARM: dts: imx6ul: add missing properties for sram ext2: Add more validity checks for inode counts USB: HCD: Fix URB giveback issue in tasklet function arm64: fix oops in concurrently setting insn_emulation sysctls arm64: Do not forget syscall when starting a new thread. netfilter: nf_tables: fix null deref due to zeroed list head netfilter: nf_tables: do not allow SET_ID to refer to another table MIPS: cpuinfo: Fix a warning for CONFIG_CPUMASK_OFFSTACK powerpc/powernv: Avoid crashing if rng is NULL powerpc/fsl-pci: Fix Class Code of PCIe Root Port PCI: Add defines for normal and subtractive PCI bridges ia64, processor: fix -Wincompatible-pointer-types in ia64_get_irr() md-raid10: fix KASAN warning serial: mvebu-uart: uart2 error bits clearing fuse: limit nsec iio: light: isl29028: Fix the warning in isl29028_remove() bpf: Verifer, adjust_scalar_min_max_vals to always call update_reg_bounds() drm/amdgpu: Check BO's requested pinning domains against its preferred_domains drm/nouveau: fix another off-by-one in nvbios_addr parisc: Fix device names in /proc/iomem ovl: drop WARN_ON() dentry is NULL in ovl_encode_fh() usbnet: Fix linkwatch use-after-free on disconnect fbcon: Fix boundary checks for fbcon=vc:n1-n2 parameters thermal: sysfs: Fix cooling_device_stats_setup() error code path fs: Add missing umask strip in vfs_tmpfile vfs: Check the truncate maximum size in inode_newsize_ok() tty: vt: initialize unicode screen buffer ALSA: hda/cirrus - support for iMac 12,1 model ALSA: hda/conexant: Add quirk for LENOVO 20149 Notebook model KVM: x86: Set error code to segment selector on LLDT/LTR non-canonical #GP KVM: x86: Mark TSS busy during LTR emulation _after_ all fault checks KVM: SVM: Don't BUG if userspace injects an interrupt with GIF=0 HID: wacom: Don't register pad_input for touch switch add barriers to buffer_uptodate and set_buffer_uptodate wifi: mac80211_hwsim: use 32-bit skb cookie wifi: mac80211_hwsim: add back erroneously removed cast wifi: mac80211_hwsim: fix race condition in pending packet ALSA: bcd2000: Fix a UAF bug on the error path of probing x86: link vdso and boot with -z noexecstack --no-warn-rwx-segments Makefile: link with -z noexecstack --no-warn-rwx-segments Change-Id: Ibfdbdf88770193213d228f96ea0fd937b1eb8409 Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
320 lines
8.6 KiB
C
320 lines
8.6 KiB
C
/*
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* Based on arch/arm/include/asm/processor.h
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*
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* Copyright (C) 1995-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PROCESSOR_H
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#define __ASM_PROCESSOR_H
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#define TASK_SIZE_64 (UL(1) << VA_BITS)
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#define KERNEL_DS UL(-1)
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#define USER_DS (TASK_SIZE_64 - 1)
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#ifndef __ASSEMBLY__
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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#ifdef __KERNEL__
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#include <linux/build_bug.h>
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#include <linux/cache.h>
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#include <linux/init.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <vdso/processor.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/lse.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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/*
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* TASK_SIZE - the maximum size of a user space task.
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* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
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*/
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#ifdef CONFIG_COMPAT
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#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
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/*
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* With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
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* by the compat vectors page.
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*/
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#define TASK_SIZE_32 UL(0x100000000)
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#else
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#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
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#endif /* CONFIG_ARM64_64K_PAGES */
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#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
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TASK_SIZE_32 : TASK_SIZE_64)
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#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
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TASK_SIZE_32 : TASK_SIZE_64)
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#else
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#define TASK_SIZE TASK_SIZE_64
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#endif /* CONFIG_COMPAT */
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
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#define STACK_TOP_MAX TASK_SIZE_64
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#ifdef CONFIG_COMPAT
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#define AARCH32_VECTORS_BASE 0xffff0000
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#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
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AARCH32_VECTORS_BASE : STACK_TOP_MAX)
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#else
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#define STACK_TOP STACK_TOP_MAX
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#endif /* CONFIG_COMPAT */
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extern phys_addr_t arm64_dma_phys_limit;
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#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
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extern unsigned int boot_reason;
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extern unsigned int cold_boot;
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struct debug_info {
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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/* Have we suspended stepping by a debugger? */
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int suspended_step;
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/* Allow breakpoints and watchpoints to be disabled for this thread. */
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int bps_disabled;
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int wps_disabled;
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/* Hardware breakpoints pinned to this task. */
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struct perf_event *hbp_break[ARM_MAX_BRP];
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struct perf_event *hbp_watch[ARM_MAX_WRP];
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#endif
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};
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struct cpu_context {
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unsigned long x19;
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unsigned long x20;
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unsigned long x21;
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unsigned long x22;
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unsigned long x23;
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unsigned long x24;
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unsigned long x25;
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unsigned long x26;
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unsigned long x27;
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unsigned long x28;
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unsigned long fp;
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unsigned long sp;
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unsigned long pc;
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};
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struct thread_struct {
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struct cpu_context cpu_context; /* cpu context */
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/*
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* Whitelisted fields for hardened usercopy:
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* Maintainers must ensure manually that this contains no
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* implicit padding.
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*/
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struct {
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unsigned long tp_value; /* TLS register */
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unsigned long tp2_value;
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struct user_fpsimd_state fpsimd_state;
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} uw;
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unsigned int fpsimd_cpu;
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void *sve_state; /* SVE registers, if any */
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unsigned int sve_vl; /* SVE vector length */
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unsigned int sve_vl_onexec; /* SVE vl after next exec */
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unsigned long fault_address; /* fault info */
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unsigned long fault_code; /* ESR_EL1 value */
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struct debug_info debug; /* debugging */
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};
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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unsigned long *size)
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{
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/* Verify that there is no padding among the whitelisted fields: */
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BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
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sizeof_field(struct thread_struct, uw.tp_value) +
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sizeof_field(struct thread_struct, uw.tp2_value) +
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sizeof_field(struct thread_struct, uw.fpsimd_state));
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*offset = offsetof(struct thread_struct, uw);
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*size = sizeof_field(struct thread_struct, uw);
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}
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#ifdef CONFIG_COMPAT
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#define task_user_tls(t) \
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({ \
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unsigned long *__tls; \
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if (is_compat_thread(task_thread_info(t))) \
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__tls = &(t)->thread.uw.tp2_value; \
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else \
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__tls = &(t)->thread.uw.tp_value; \
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__tls; \
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})
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#else
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#define task_user_tls(t) (&(t)->thread.uw.tp_value)
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#endif
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/* Sync TPIDR_EL0 back to thread_struct for current */
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void tls_preserve_current_state(void);
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#define INIT_THREAD { \
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.fpsimd_cpu = NR_CPUS, \
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}
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static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
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{
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s32 previous_syscall = regs->syscallno;
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memset(regs, 0, sizeof(*regs));
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regs->syscallno = previous_syscall;
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regs->pc = pc;
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}
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static inline void set_ssbs_bit(struct pt_regs *regs)
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{
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regs->pstate |= PSR_SSBS_BIT;
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}
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static inline void set_compat_ssbs_bit(struct pt_regs *regs)
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{
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regs->pstate |= PSR_AA32_SSBS_BIT;
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}
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static inline void start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = PSR_MODE_EL0t;
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if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
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set_ssbs_bit(regs);
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regs->sp = sp;
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}
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#ifdef CONFIG_COMPAT
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static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = PSR_AA32_MODE_USR;
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if (pc & 1)
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regs->pstate |= PSR_AA32_T_BIT;
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#ifdef __AARCH64EB__
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regs->pstate |= PSR_AA32_E_BIT;
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#endif
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if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
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set_compat_ssbs_bit(regs);
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regs->compat_sp = sp;
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}
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#endif
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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unsigned long get_wchan(struct task_struct *p);
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/* Thread switching */
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extern struct task_struct *cpu_switch_to(struct task_struct *prev,
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struct task_struct *next);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
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#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
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/*
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* Prefetching support
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*/
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *ptr)
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{
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asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_PREFETCHW
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static inline void prefetchw(const void *ptr)
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{
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asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void spin_lock_prefetch(const void *ptr)
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{
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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"prfm pstl1strm, %a0",
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"nop") : : "p" (ptr));
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}
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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#endif
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void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
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void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
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void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);
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extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
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extern void __init minsigstksz_setup(void);
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/*
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* Not at the top of the file due to a direct #include cycle between
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* <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
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* ensures that contents of processor.h are visible to fpsimd.h even if
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* processor.h is included first.
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*
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* These prctl helpers are the only things in this file that require
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* fpsimd.h. The core code expects them to be in this header.
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*/
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#include <asm/fpsimd.h>
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/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
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#define SVE_SET_VL(arg) sve_set_current_vl(arg)
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#define SVE_GET_VL() sve_get_current_vl()
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#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
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/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
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long set_tagged_addr_ctrl(unsigned long arg);
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long get_tagged_addr_ctrl(void);
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#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(arg)
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#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl()
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#endif
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/*
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* For CONFIG_GCC_PLUGIN_STACKLEAK
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*
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* These need to be macros because otherwise we get stuck in a nightmare
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* of header definitions for the use of task_stack_page.
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*/
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#define current_top_of_stack() \
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({ \
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struct stack_info _info; \
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BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info)); \
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_info.high; \
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})
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#define on_thread_stack() (on_task_stack(current, current_stack_pointer, NULL))
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PROCESSOR_H */
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