e6c876d8b8
https://source.android.com/security/bulletin/2021-08-01 CVE-2020-14381 CVE-2021-3347 CVE-2021-28375 * tag 'ASB-2021-08-05_4.19-stable' of https://github.com/aosp-mirror/kernel_common: Linux 4.19.200 ARM: dts: versatile: Fix up interrupt controller node names cifs: fix the out of range assignment to bit fields in parse_server_interfaces firmware: arm_scmi: Fix range check for the maximum number of pending messages firmware: arm_scmi: Fix possible scmi_linux_errmap buffer overflow hfs: add lock nesting notation to hfs_find_init hfs: fix high memory mapping in hfs_bnode_read hfs: add missing clean-up in hfs_fill_super sctp: move 198 addresses from unusable to private scope net: annotate data race around sk_ll_usec net/802/garp: fix memleak in garp_request_join() net/802/mrp: fix memleak in mrp_request_join() workqueue: fix UAF in pwq_unbound_release_workfn() af_unix: fix garbage collect vs MSG_PEEK net: split out functions related to registering inflight socket files KVM: x86: determine if an exception has an error code only when injecting it. iio: dac: ds4422/ds4424 drop of_node check selftest: fix build error in tools/testing/selftests/vm/userfaultfd.c ANDROID: staging: ion: move buffer kmap from begin/end_cpu_access() Linux 4.19.199 xhci: add xhci_get_virt_ep() helper spi: spi-fsl-dspi: Fix a resource leak in an error handling path PCI: Mark AMD Navi14 GPU ATS as broken btrfs: compression: don't try to compress if we don't have enough pages iio: accel: bma180: Fix BMA25x bandwidth register values iio: accel: bma180: Use explicit member assignment net: bcmgenet: ensure EXT_ENERGY_DET_MASK is clear net: dsa: mv88e6xxx: use correct .stats_set_histogram() on Topaz KVM: Use kvm_pfn_t for local PFN variable in hva_to_pfn_remapped() KVM: do not allow mapping valid but non-reference-counted pages KVM: do not assume PTE is writable after follow_pfn drm: Return -ENOTTY for non-drm ioctls nds32: fix up stack guard gap selftest: use mmap instead of posix_memalign to allocate memory ixgbe: Fix packet corruption due to missing DMA sync media: ngene: Fix out-of-bounds bug in ngene_command_config_free_buf() tracing: Fix bug in rb_per_cpu_empty() that might cause deadloop. usb: dwc2: gadget: Fix sending zero length packet in DDMA mode. USB: serial: cp210x: add ID for CEL EM3588 USB ZigBee stick USB: serial: cp210x: fix comments for GE CS1000 USB: serial: option: add support for u-blox LARA-R6 family usb: renesas_usbhs: Fix superfluous irqs happen after usb_pkt_pop() usb: max-3421: Prevent corruption of freed memory USB: usb-storage: Add LaCie Rugged USB3-FW to IGNORE_UAS usb: hub: Fix link power management max exit latency (MEL) calculations usb: hub: Disable USB 3 device initiated lpm if exit latency is too high KVM: PPC: Book3S: Fix H_RTAS rets buffer overflow xhci: Fix lost USB 2 remote wake ALSA: sb: Fix potential ABBA deadlock in CSP driver ALSA: usb-audio: Add registration quirk for JBL Quantum headsets s390/ftrace: fix ftrace_update_ftrace_func implementation Revert "MIPS: add PMD table accounting into MIPS'pmd_alloc_one" proc: Avoid mixing integer types in mem_rw() drm/panel: raspberrypi-touchscreen: Prevent double-free net: sched: cls_api: Fix the the wrong parameter sctp: update active_key for asoc when old key is being replaced Revert "USB: quirks: ignore remote wake-up on Fibocom L850-GL LTE modem" nvme-pci: don't WARN_ON in nvme_reset_work if ctrl.state is not RESETTING net/sched: act_skbmod: Skip non-Ethernet packets net/tcp_fastopen: fix data races around tfo_active_disable_stamp spi: cadence: Correct initialisation of runtime PM again scsi: target: Fix protect handling in WRITE SAME(32) scsi: iscsi: Fix iface sysfs attr detection netrom: Decrease sock refcount when sock timers expire KVM: PPC: Fix kvm_arch_vcpu_ioctl vcpu_load leak net: decnet: Fix sleeping inside in af_decnet net: fix uninit-value in caif_seqpkt_sendmsg bpftool: Check malloc return value in mount_bpffs_for_pin s390/bpf: Perform r1 range checking before accessing jit->seen_reg[r1] liquidio: Fix unintentional sign extension issue on left shift of u16 spi: mediatek: fix fifo rx mode perf probe-file: Delete namelist in del_events() on the error path perf test bpf: Free obj_buf perf lzma: Close lzma stream on exit perf dso: Fix memory leak in dso__new_map() perf probe: Fix dso->nsinfo refcounting perf map: Fix dso->nsinfo refcounting nvme-pci: do not call nvme_dev_remove_admin from nvme_remove ipv6: fix 'disable_policy' for fwd packets igb: Fix position of assignment to *ring igb: Check if num of q_vectors is smaller than max before array access iavf: Fix an error handling path in 'iavf_probe()' e1000e: Fix an error handling path in 'e1000_probe()' fm10k: Fix an error handling path in 'fm10k_probe()' igb: Fix an error handling path in 'igb_probe()' ixgbe: Fix an error handling path in 'ixgbe_probe()' igb: Fix use-after-free error during reset net: ip_tunnel: fix mtu calculation for ETHER tunnel devices udp: annotate data races around unix_sk(sk)->gso_size bpftool: Properly close va_list 'ap' by va_end() on error ipv6: tcp: drop silly ICMPv6 packet too big messages tcp: annotate data races around tp->mtu_info dma-buf/sync_file: Don't leak fences on merge failure net: validate lwtstate->data before returning from skb_tunnel_info() net: send SYNACK packet with accepted fwmark net: ti: fix UAF in tlan_remove_one net: qcom/emac: fix UAF in emac_remove net: moxa: fix UAF in moxart_mac_probe net: bcmgenet: Ensure all TX/RX queues DMAs are disabled net: bridge: sync fdb to new unicast-filtering ports netfilter: ctnetlink: suspicious RCU usage in ctnetlink_dump_helpinfo net: ipv6: fix return value of ip6_skb_dst_mtu net: dsa: mv88e6xxx: enable .rmu_disable() on Topaz dm writecache: fix writing beyond end of underlying device when shrinking dm writecache: return the exact table values that were set mm: slab: fix kmem_cache_create failed when sysfs node not destroyed sched/fair: Fix CFS bandwidth hrtimer expiry type scsi: libfc: Fix array index out of bound exception scsi: libsas: Add LUN number check in .slave_alloc callback scsi: aic7xxx: Fix unintentional sign extension issue on left shift of u8 rtc: max77686: Do not enforce (incorrect) interrupt trigger type kbuild: mkcompile_h: consider timestamp if KBUILD_BUILD_TIMESTAMP is set thermal/core: Correct function name thermal_zone_device_unregister() arm64: dts: ls208xa: remove bus-num from dspi node soc/tegra: fuse: Fix Tegra234-only builds ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 ARM: dts: stm32: fix i2c node name on stm32f746 to prevent warnings ARM: dts: rockchip: fix supply properties in io-domains nodes arm64: dts: juno: Update SCPI nodes as per the YAML schema ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings ARM: dts: stm32: fix RCC node name on stm32f429 MCU ARM: dts: stm32: fix gpio-keys node on STM32 MCU boards rtc: mxc_v2: add missing MODULE_DEVICE_TABLE ARM: imx: pm-imx5: Fix references to imx5_cpu_suspend_info ARM: dts: imx6: phyFLEX: Fix UART hardware flow control ARM: dts: Hurricane 2: Fix NAND nodes names ARM: dts: BCM63xx: Fix NAND nodes names ARM: NSP: dts: fix NAND nodes names ARM: Cygnus: dts: fix NAND nodes names ARM: brcmstb: dts: fix NAND nodes names reset: ti-syscon: fix to_ti_syscon_reset_data macro arm64: dts: rockchip: Fix power-controller node names for rk3328 ARM: dts: rockchip: Fix power-controller node names for rk3288 ARM: dts: rockchip: Fix IOMMU nodes properties on rk322x ARM: dts: rockchip: Fix the timer clocks order arm64: dts: rockchip: fix pinctrl sleep nodename for rk3399.dtsi ARM: dts: rockchip: fix pinctrl sleep nodename for rk3036-kylin and rk3288 ARM: dts: gemini: add device_type on pci ARM: dts: gemini: rename mdio to the right name ANDROID: generate_initcall_order.pl: Use two dash long options for llvm-nm Revert "media: subdev: disallow ioctl for saa6588/davinci" ANDROID: GKI: fix up crc change in ip.h Linux 4.19.198 seq_file: disallow extremely large seq buffer allocations scsi: scsi_dh_alua: Fix signedness bug in alua_rtpg() net: bridge: multicast: fix PIM hello router port marking race MIPS: vdso: Invalid GIC access through VDSO mips: disable branch profiling in boot/decompress.o mips: always link byteswap helpers into decompressor scsi: be2iscsi: Fix an error handling path in beiscsi_dev_probe() ARM: dts: imx6q-dhcom: Add gpios pinctrl for i2c bus recovery ARM: dts: imx6q-dhcom: Fix ethernet plugin detection problems ARM: dts: imx6q-dhcom: Fix ethernet reset time properties ARM: dts: am437x: align ti,pindir-d0-out-d1-in property with dt-shema ARM: dts: am335x: align ti,pindir-d0-out-d1-in property with dt-shema memory: fsl_ifc: fix leak of private memory on probe failure memory: fsl_ifc: fix leak of IO mapping on probe failure reset: bail if try_module_get() fails ARM: dts: BCM5301X: Fixup SPI binding ARM: dts: r8a7779, marzen: Fix DU clock names arm64: dts: renesas: v3msk: Fix memory size rtc: fix snprintf() checking in is_rtc_hctosys() memory: atmel-ebi: add missing of_node_put for loop iteration ARM: dts: exynos: fix PWM LED max brightness on Odroid XU4 ARM: dts: exynos: fix PWM LED max brightness on Odroid HC1 ARM: dts: exynos: fix PWM LED max brightness on Odroid XU/XU3 reset: a10sr: add missing of_match_table reference hexagon: use common DISCARDS macro NFSv4/pNFS: Don't call _nfs4_pnfs_v3_ds_connect multiple times ALSA: isa: Fix error return code in snd_cmi8330_probe() virtio_net: move tx vq operation under tx queue lock x86/fpu: Limit xstate copy size in xstateregs_set() PCI: iproc: Support multi-MSI only on uniprocessor kernel PCI: iproc: Fix multi-MSI base vector number allocation ubifs: Set/Clear I_LINKABLE under i_lock for whiteout inode nfs: fix acl memory leak of posix_acl_create() watchdog: aspeed: fix hardware timeout calculation um: fix error return code in winch_tramp() um: fix error return code in slip_open() NFSv4: Initialise connection to the server in nfs4_alloc_client() power: supply: rt5033_battery: Fix device tree enumeration PCI/sysfs: Fix dsm_label_utf16s_to_utf8s() buffer overrun f2fs: add MODULE_SOFTDEP to ensure crc32 is included in the initramfs virtio_console: Assure used length from device is limited virtio_net: Fix error handling in virtnet_restore() virtio-blk: Fix memory leak among suspend/resume procedure ACPI: video: Add quirk for the Dell Vostro 3350 ACPI: AMBA: Fix resource name in /proc/iomem pwm: tegra: Don't modify HW state in .remove callback power: supply: ab8500: add missing MODULE_DEVICE_TABLE power: supply: charger-manager: add missing MODULE_DEVICE_TABLE NFS: nfs_find_open_context() may only select open files ceph: remove bogus checks and WARN_ONs from ceph_set_page_dirty orangefs: fix orangefs df output. PCI: tegra: Add missing MODULE_DEVICE_TABLE x86/fpu: Return proper error codes from user access functions watchdog: iTCO_wdt: Account for rebooting on second timeout watchdog: Fix possible use-after-free by calling del_timer_sync() watchdog: sc520_wdt: Fix possible use-after-free in wdt_turnoff() watchdog: Fix possible use-after-free in wdt_startup() ARM: 9087/1: kprobes: test-thumb: fix for LLVM_IAS=1 power: reset: gpio-poweroff: add missing MODULE_DEVICE_TABLE power: supply: max17042: Do not enforce (incorrect) interrupt trigger type power: supply: ab8500: Avoid NULL pointers pwm: spear: Don't modify HW state in .remove callback lib/decompress_unlz4.c: correctly handle zero-padding around initrds. i2c: core: Disable client irq on reboot/shutdown intel_th: Wait until port is in reset before programming it staging: rtl8723bs: fix macro value for 2.4Ghz only device ALSA: hda: Add IRQ check for platform_get_irq() backlight: lm3630a: Fix return code of .update_status() callback powerpc/boot: Fixup device-tree on little endian usb: gadget: hid: fix error return code in hid_bind() usb: gadget: f_hid: fix endianness issue with descriptors ALSA: bebob: add support for ToneWeal FW66 Input: hideep - fix the uninitialized use in hideep_nvm_unlock() ASoC: soc-core: Fix the error return code in snd_soc_of_parse_audio_routing() gpio: pca953x: Add support for the On Semi pca9655 selftests/powerpc: Fix "no_handler" EBB selftest ALSA: ppc: fix error return code in snd_pmac_probe() gpio: zynq: Check return value of pm_runtime_get_sync powerpc/ps3: Add dma_mask to ps3_dma_region ALSA: sb: Fix potential double-free of CSP mixer elements selftests: timers: rtcpie: skip test if default RTC device does not exist s390/sclp_vt220: fix console name to match device mfd: da9052/stmpe: Add and modify MODULE_DEVICE_TABLE scsi: qedi: Fix null ref during abort handling scsi: iscsi: Fix shost->max_id use scsi: iscsi: Fix conn use after free during resets scsi: iscsi: Add iscsi_cls_conn refcount helpers fs/jfs: Fix missing error code in lmLogInit() scsi: scsi_dh_alua: Check for negative result value tty: serial: 8250: serial_cs: Fix a memory leak in error handling path ALSA: ac97: fix PM reference leak in ac97_bus_remove() scsi: core: Cap scsi_host cmd_per_lun at can_queue scsi: lpfc: Fix crash when lpfc_sli4_hba_setup() fails to initialize the SGLs scsi: lpfc: Fix "Unexpected timeout" error in direct attach topology w1: ds2438: fixing bug that would always get page0 Revert "ALSA: bebob/oxfw: fix Kconfig entry for Mackie d.2 Pro" misc/libmasm/module: Fix two use after free in ibmasm_init_one tty: serial: fsl_lpuart: fix the potential risk of division or modulo by zero PCI: aardvark: Fix kernel panic during PIO transfer PCI: aardvark: Don't rely on jiffies while holding spinlock tracing: Do not reference char * as a string in histograms scsi: core: Fix bad pointer dereference when ehandler kthread is invalid KVM: X86: Disable hardware breakpoints unconditionally before kvm_x86->run() KVM: x86: Use guest MAXPHYADDR from CPUID.0x8000_0008 iff TDP is enabled smackfs: restrict bytes count in smk_set_cipso() jfs: fix GPF in diFree pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() media: uvcvideo: Fix pixel format change for Elgato Cam Link 4K media: gspca/sunplus: fix zero-length control requests media: gspca/sq905: fix control-request direction media: zr364xx: fix memory leak in zr364xx_start_readpipe media: dtv5100: fix control-request directions media: subdev: disallow ioctl for saa6588/davinci PCI: aardvark: Fix checking for PIO Non-posted Request PCI: Leave Apple Thunderbolt controllers on for s2idle or standby dm btree remove: assign new_root only when removal succeeds coresight: tmc-etf: Fix global-out-of-bounds in tmc_update_etf_buffer() ipack/carriers/tpci200: Fix a double free in tpci200_pci_probe tracing: Resize tgid_map to pid_max, not PID_MAX_DEFAULT tracing: Simplify & fix saved_tgids logic seq_buf: Fix overflow in seq_buf_putmem_hex() power: supply: ab8500: Fix an old bug ipmi/watchdog: Stop watchdog timer when the current action is 'none' qemu_fw_cfg: Make fw_cfg_rev_attr a proper kobj_attribute ASoC: tegra: Set driver_name=tegra for all machine drivers clocksource/arm_arch_timer: Improve Allwinner A64 timer workaround cpu/hotplug: Cure the cpusets trainwreck ata: ahci_sunxi: Disable DIPM mmc: core: Allow UHS-I voltage switch for SDSC cards if supported mmc: core: clear flags before allowing to retune mmc: sdhci: Fix warning message when accessing RPMB in HS400 mode drm/msm/mdp4: Fix modifier support enabling pinctrl/amd: Add device HID for new AMD GPIO controller drm/amd/display: fix incorrrect valid irq check drm/radeon: Add the missed drm_gem_object_put() in radeon_user_framebuffer_create() usb: gadget: f_fs: Fix setting of device and driver data cross-references powerpc/barrier: Avoid collision with clang's __lwsync macro fuse: reject internal errno serial: mvebu-uart: fix calculation of clock divisor serial: mvebu-uart: clarify the baud rate derivation bdi: Do not use freezable workqueue fscrypt: don't ignore minor_hash when hash is 0 MIPS: set mips32r5 for virt extensions sctp: add size validation when walking chunks sctp: validate from_addr_param return Bluetooth: btusb: fix bt fiwmare downloading failure issue for qca btsoc. Bluetooth: Shutdown controller after workqueues are flushed or cancelled Bluetooth: Fix the HCI to MGMT status conversion table RDMA/cma: Fix rdma_resolve_route() memory leak net: ip: avoid OOM kills with large UDP sends over loopback media, bpf: Do not copy more entries than user space requested wireless: wext-spy: Fix out-of-bounds warning sfc: error code if SRIOV cannot be disabled sfc: avoid double pci_remove of VFs iwlwifi: pcie: free IML DMA memory allocation iwlwifi: mvm: don't change band on bound PHY contexts RDMA/rxe: Don't overwrite errno from ib_umem_get() vsock: notify server to shutdown when client has pending signal atm: nicstar: register the interrupt handler in the right place atm: nicstar: use 'dma_free_coherent' instead of 'kfree' MIPS: add PMD table accounting into MIPS'pmd_alloc_one rtl8xxxu: Fix device info for RTL8192EU devices net: fix mistake path for netdev_features_strings cw1200: add missing MODULE_DEVICE_TABLE wl1251: Fix possible buffer overflow in wl1251_cmd_scan wlcore/wl12xx: Fix wl12xx get_mac error if device is in ELP xfrm: Fix error reporting in xfrm_state_construct. selinux: use __GFP_NOWARN with GFP_NOWAIT in the AVC fjes: check return value after calling platform_get_resource() net: micrel: check return value after calling platform_get_resource() net: mvpp2: check return value after calling platform_get_resource() net: bcmgenet: check return value after calling platform_get_resource() virtio_net: Remove BUG() to avoid machine dead ice: set the value of global config lock timeout longer pinctrl: mcp23s08: fix race condition in irq handler dm space maps: don't reset space map allocation cursor when committing RDMA/cxgb4: Fix missing error code in create_qp() ipv6: use prandom_u32() for ID generation clk: tegra: Ensure that PLLU configuration is applied properly clk: renesas: r8a77995: Add ZA2 clock e100: handle eeprom as little endian udf: Fix NULL pointer dereference in udf_symlink function drm/virtio: Fix double free on probe failure reiserfs: add check for invalid 1st journal block net: Treat __napi_schedule_irqoff() as __napi_schedule() on PREEMPT_RT atm: nicstar: Fix possible use-after-free in nicstar_cleanup() mISDN: fix possible use-after-free in HFC_cleanup() atm: iphase: fix possible use-after-free in ia_module_exit() hugetlb: clear huge pte during flush function on mips platform drm/amd/display: fix use_max_lb flag for 420 pixel formats net: pch_gbe: Use proper accessors to BE data in pch_ptp_match() drm/amd/amdgpu/sriov disable all ip hw status by default drm/zte: Don't select DRM_KMS_FB_HELPER drm/mxsfb: Don't select DRM_KMS_FB_HELPER mmc: vub3000: fix control-request direction mmc: block: Disable CMDQ on the ioctl path perf llvm: Return -ENOMEM when asprintf() fails selftests/vm/pkeys: fix alloc_random_pkey() to make it really, really random mm/huge_memory.c: don't discard hugepage if other processes are mapping it vfio/pci: Handle concurrent vma faults arm64: dts: marvell: armada-37xx: Fix reg for standard variant of UART serial: mvebu-uart: correctly calculate minimal possible baudrate powerpc: Offline CPU in stop_this_cpu() leds: ktd2692: Fix an error handling path leds: as3645a: Fix error return code in as3645a_parse_node() configfs: fix memleak in configfs_release_bin_file ASoC: atmel-i2s: Fix usage of capture and playback at the same time extcon: max8997: Add missing modalias string extcon: sm5502: Drop invalid register write in sm5502_reg_data phy: ti: dm816x: Fix the error handling path in 'dm816x_usb_phy_probe() scsi: mpt3sas: Fix error return value in _scsih_expander_add() mtd: rawnand: marvell: add missing clk_disable_unprepare() on error in marvell_nfc_resume() of: Fix truncation of memory sizes on 32-bit platforms ASoC: cs42l42: Correct definition of CS42L42_ADC_PDN_MASK iio: prox: isl29501: Fix buffer alignment in iio_push_to_buffers_with_timestamp() serial: 8250: Actually allow UPF_MAGIC_MULTIPLIER baud rates staging: mt7621-dts: fix pci address for PCI memory range staging: gdm724x: check for overflow in gdm_lte_netif_rx() staging: gdm724x: check for buffer overflow in gdm_lte_multi_sdu_pkt() iio: adc: ti-ads8688: Fix alignment of buffer in iio_push_to_buffers_with_timestamp() iio: adc: mxs-lradc: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: adc: hx711: Fix buffer alignment in iio_push_to_buffers_with_timestamp() eeprom: idt_89hpesx: Restore printing the unsupported fwnode name eeprom: idt_89hpesx: Put fwnode in matching case during ->probe() s390: appldata depends on PROC_SYSCTL visorbus: fix error return code in visorchipset_init() fsi/sbefifo: Fix reset timeout fsi/sbefifo: Clean up correct FIFO when receiving reset request from SBE fsi: scom: Reset the FSI2PIB engine for any error fsi: core: Fix return of error values on failures scsi: FlashPoint: Rename si_flags field tty: nozomi: Fix the error handling path of 'nozomi_card_init()' char: pcmcia: error out if 'num_bytes_read' is greater than 4 in set_protocol() Input: hil_kbd - fix error return code in hil_dev_connect() ASoC: rsnd: tidyup loop on rsnd_adg_clk_query() ASoC: hisilicon: fix missing clk_disable_unprepare() on error in hi6210_i2s_startup() iio: potentiostat: lmp91000: Fix alignment of buffer in iio_push_to_buffers_with_timestamp() iio: light: tcs3472: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: light: tcs3414: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: light: isl29125: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: prox: as3935: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: prox: pulsed-light: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: prox: srf08: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: humidity: am2315: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: gyro: bmg160: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: adc: vf610: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: adc: ti-ads1015: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: stk8ba50: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: stk8312: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: kxcjk-1013: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: hid: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: bma220: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: accel: bma180: Fix buffer alignment in iio_push_to_buffers_with_timestamp() iio: adis_buffer: do not return ints in irq handlers mwifiex: re-fix for unaligned accesses tty: nozomi: Fix a resource leak in an error handling function RDMA/mlx5: Don't access NULL-cleared mpi pointer net: sched: fix warning in tcindex_alloc_perfect_hash net: lwtunnel: handle MTU calculation in forwading writeback: fix obtain a reference to a freeing memcg css Bluetooth: Fix handling of HCI_LE_Advertising_Set_Terminated event Bluetooth: mgmt: Fix slab-out-of-bounds in tlv_data_is_valid ipv6: fix out-of-bound access in ip6_parse_tlv() ibmvnic: free tx_pool if tso_pool alloc fails Revert "ibmvnic: remove duplicate napi_schedule call in open function" i40e: Fix autoneg disabling for non-10GBaseT links i40e: Fix error handling in i40e_vsi_open bpf: Do not change gso_size during bpf_skb_change_proto() ipv6: exthdrs: do not blindly use init_net net: bcmgenet: Fix attaching to PYH failed on RPi 4B mac80211: remove iwlwifi specific workaround NDPs of null_response ieee802154: hwsim: avoid possible crash in hwsim_del_edge_nl() ieee802154: hwsim: Fix memory leak in hwsim_add_one net/ipv4: swap flow ports when validating source vxlan: add missing rcu_read_lock() in neigh_reduce() pkt_sched: sch_qfq: fix qfq_change_class() error path net: ethernet: ezchip: fix error handling net: ethernet: ezchip: fix UAF in nps_enet_remove net: ethernet: aeroflex: fix UAF in greth_of_remove samples/bpf: Fix the error return code of xdp_redirect's main() RDMA/rxe: Fix qp reference counting for atomic ops netfilter: nft_tproxy: restrict support to TCP and UDP transport protocols netfilter: nft_osf: check for TCP packet before further processing netfilter: nft_exthdr: check for IPv6 packet before further processing RDMA/mlx5: Don't add slave port to unaffiliated list netlabel: Fix memory leak in netlbl_mgmt_add_common ath10k: Fix an error code in ath10k_add_interface() brcmsmac: mac80211_if: Fix a resource leak in an error handling path brcmfmac: correctly report average RSSI in station info brcmfmac: fix setting of station info chains bitmask ssb: Fix error return code in ssb_bus_scan() wcn36xx: Move hal_buf allocation to devm_kmalloc in probe ieee802154: hwsim: Fix possible memory leak in hwsim_subscribe_all_others wireless: carl9170: fix LEDS build errors & warnings tools/bpftool: Fix error return code in do_batch() drm: qxl: ensure surf.data is ininitialized RDMA/rxe: Fix failure during driver load ehea: fix error return code in ehea_restart_qps() drm/rockchip: cdn-dp-core: add missing clk_disable_unprepare() on error in cdn_dp_grf_write() net: pch_gbe: Propagate error from devm_gpio_request_one() net: mvpp2: Put fwnode in error case during ->probe() ocfs2: fix snprintf() checking blk-wbt: make sure throttle is enabled properly blk-wbt: introduce a new disable state to prevent false positive by rwb_enabled() ACPI: sysfs: Fix a buffer overrun problem with description_show() crypto: nx - Fix RCU warning in nx842_OF_upd_status spi: spi-sun6i: Fix chipselect/clock bug btrfs: clear log tree recovering status if starting transaction fails hwmon: (max31790) Fix fan speed reporting for fan7..12 hwmon: (max31722) Remove non-standard ACPI device IDs media: s5p-g2d: Fix a memory leak on ctx->fh.m2m_ctx mmc: usdhi6rol0: fix error return code in usdhi6_probe() media: siano: Fix out-of-bounds warnings in smscore_load_firmware_family2() media: gspca/gl860: fix zero-length control requests media: tc358743: Fix error return code in tc358743_probe_of() media: exynos4-is: Fix a use after free in isp_video_release pata_ep93xx: fix deferred probing media: rc: i2c: Fix an error message crypto: ccp - Fix a resource leak in an error handling path evm: fix writing <securityfs>/evm overflow pata_octeon_cf: avoid WARN_ON() in ata_host_activate() media: I2C: change 'RST' to "RSET" to fix multiple build errors pata_rb532_cf: fix deferred probing sata_highbank: fix deferred probing crypto: ux500 - Fix error return code in hash_hw_final() crypto: ixp4xx - dma_unmap the correct address media: s5p_cec: decrement usage count if disabled ia64: mca_drv: fix incorrect array size calculation HID: wacom: Correct base usage for capacitive ExpressKey status bits ACPI: tables: Add custom DSDT file as makefile prerequisite clocksource: Retry clock read if long delays detected platform/x86: toshiba_acpi: Fix missing error code in toshiba_acpi_setup_keyboard() ACPI: bus: Call kobject_put() in acpi_init() error path ACPICA: Fix memory leak caused by _CID repair function fs: dlm: fix memory leak when fenced random32: Fix implicit truncation warning in prandom_seed_state() fs: dlm: cancel work sync othercon block_dump: remove block_dump feature in mark_inode_dirty() ACPI: EC: Make more Asus laptops use ECDT _GPE lib: vsprintf: Fix handling of number field widths in vsscanf hv_utils: Fix passing zero to 'PTR_ERR' warning ACPI: processor idle: Fix up C-state latency if not ordered EDAC/ti: Add missing MODULE_DEVICE_TABLE HID: do not use down_interruptible() when unbinding devices regulator: da9052: Ensure enough delay time for .set_voltage_time_sel btrfs: disable build on platforms having page size 256K btrfs: abort transaction if we fail to update the delayed inode btrfs: fix error handling in __btrfs_update_delayed_inode media: imx-csi: Skip first few frames from a BT.656 source media: siano: fix device register error path media: dvb_net: avoid speculation from net slot crypto: shash - avoid comparing pointers to exported functions under CFI mmc: via-sdmmc: add a check against NULL pointer dereference media: dvd_usb: memory leak in cinergyt2_fe_attach media: st-hva: Fix potential NULL pointer dereferences media: bt8xx: Fix a missing check bug in bt878_probe media: v4l2-core: Avoid the dangling pointer in v4l2_fh_release media: em28xx: Fix possible memory leak of em28xx struct sched/fair: Fix ascii art by relpacing tabs crypto: qat - remove unused macro in FW loader crypto: qat - check return code of qat_hal_rd_rel_reg() media: pvrusb2: fix warning in pvr2_i2c_core_done media: cobalt: fix race condition in setting HPD media: cpia2: fix memory leak in cpia2_usb_probe crypto: nx - add missing MODULE_DEVICE_TABLE regulator: uniphier: Add missing MODULE_DEVICE_TABLE spi: omap-100k: Fix the length judgment problem spi: spi-topcliff-pch: Fix potential double free in pch_spi_process_messages() spi: spi-loopback-test: Fix 'tx_buf' might be 'rx_buf' spi: Make of_register_spi_device also set the fwnode fuse: check connected before queueing on fpq->io evm: Refuse EVM_ALLOW_METADATA_WRITES only if an HMAC key is loaded evm: Execute evm_inode_init_security() only when an HMAC key is loaded powerpc/stacktrace: Fix spurious "stale" traces in raise_backtrace_ipi() seq_buf: Make trace_seq_putmem_hex() support data longer than 8 tracepoint: Add tracepoint_probe_register_may_exist() for BPF tracing tracing/histograms: Fix parsing of "sym-offset" modifier rsi: fix AP mode with WPA failure due to encrypted EAPOL rsi: Assign beacon rate settings to the correct rate_info descriptor field ssb: sdio: Don't overwrite const buffer if block_write fails ath9k: Fix kernel NULL pointer dereference during ath_reset_internal() serial_cs: remove wrong GLOBETROTTER.cis entry serial_cs: Add Option International GSM-Ready 56K/ISDN modem serial: sh-sci: Stop dmaengine transfer in sci_stop_tx() iio: ltr501: ltr501_read_ps(): add missing endianness conversion iio: ltr501: ltr559: fix initialization of LTR501_ALS_CONTR iio: ltr501: mark register holding upper 8 bits of ALS_DATA{0,1} and PS_DATA as volatile, too iio: light: tcs3472: do not free unallocated IRQ rtc: stm32: Fix unbalanced clk_disable_unprepare() on probe error path s390/cio: dont call css_wait_for_slow_path() inside a lock SUNRPC: Should wake up the privileged task firstly. SUNRPC: Fix the batch tasks count wraparound. can: peak_pciefd: pucan_handle_status(): fix a potential starvation issue in TX path can: gw: synchronize rcu operations before removing gw job entry can: bcm: delay release of struct bcm_op after synchronize_rcu() ext4: use ext4_grp_locked_error in mb_find_extent ext4: fix avefreec in find_group_orlov ext4: remove check for zero nr_to_scan in ext4_es_scan() ext4: correct the cache_nr in tracepoint ext4_es_shrink_exit ext4: return error code when ext4_fill_flex_info() fails ext4: fix kernel infoleak via ext4_extent_header ext4: cleanup in-core orphan list if ext4_truncate() failed to get a transaction handle btrfs: clear defrag status of a root if starting transaction fails btrfs: send: fix invalid path for unlink operations after parent orphanization ARM: dts: at91: sama5d4: fix pinctrl muxing arm_pmu: Fix write counter incorrect in ARMv7 big-endian mode Input: joydev - prevent use of not validated data in JSIOCSBTNMAP ioctl iov_iter_fault_in_readable() should do nothing in xarray case ntfs: fix validity check for file name attribute xhci: solve a double free problem while doing s4 usb: typec: Add the missed altmode_id_remove() in typec_register_altmode() usb: dwc3: Fix debugfs creation flow USB: cdc-acm: blacklist Heimann USB Appset device usb: gadget: eem: fix echo command packet response issue net: can: ems_usb: fix use-after-free in ems_usb_disconnect() Input: usbtouchscreen - fix control-request directions media: dvb-usb: fix wrong definition ALSA: usb-audio: Fix OOB access at proc output ALSA: usb-audio: fix rate on Ozone Z90 USB headset scsi: core: Retry I/O for Notify (Enable Spinup) Required error Revert "clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940" Linux 4.19.197 clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940 clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support ARM: OMAP: replace setup_irq() by request_irq() KVM: SVM: Call SEV Guest Decommission if ASID binding fails xen/events: reset active flag for lateeoi events later kthread: prevent deadlock when kthread_mod_delayed_work() races with kthread_cancel_delayed_work_sync() kthread_worker: split code for canceling the delayed work timer ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment KVM: SVM: Periodically schedule when unregistering regions on destroy ext4: eliminate bogus error in ext4_data_block_valid_rcu() drm/nouveau: fix dma_address check for CPU/GPU sync scsi: sr: Return appropriate error code when disk is ejected mm, futex: fix shared futex pgoff on shmem huge page mm/thp: another PVMW_SYNC fix in page_vma_mapped_walk() mm/thp: fix page_vma_mapped_walk() if THP mapped by ptes mm: page_vma_mapped_walk(): get vma_address_end() earlier mm: page_vma_mapped_walk(): use goto instead of while (1) mm: page_vma_mapped_walk(): add a level of indentation mm: page_vma_mapped_walk(): crossing page table boundary mm: page_vma_mapped_walk(): prettify PVMW_MIGRATION block mm: page_vma_mapped_walk(): use pmde for *pvmw->pmd mm: page_vma_mapped_walk(): settle PageHuge on entry mm: page_vma_mapped_walk(): use page for pvmw->page mm: thp: replace DEBUG_VM BUG with VM_WARN when unmap fails for split mm/thp: unmap_mapping_page() to fix THP truncate_cleanup_page() mm/thp: fix page_address_in_vma() on file THP tails mm/thp: fix vma_address() if virtual address below file offset mm/thp: try_to_unmap() use TTU_SYNC for safe splitting mm/thp: make is_huge_zero_pmd() safe and quicker mm/thp: fix __split_huge_pmd_locked() on shmem migration entry mm/rmap: use page_not_mapped in try_to_unmap() mm/rmap: remove unneeded semicolon in page_not_mapped() mm: add VM_WARN_ON_ONCE_PAGE() macro Change-Id: Ia9b845672bf98427007fcdb455a467e602cfcd29 Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com> Conflicts: drivers/staging/android/ion/ion.c drivers/usb/dwc3/core.c drivers/usb/gadget/function/f_fs.c kernel/cpu.c security/selinux/avc.c
2117 lines
66 KiB
C
2117 lines
66 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
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*
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* ARMv7 support: Jean Pihet <jpihet@mvista.com>
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* 2010 (c) MontaVista Software, LLC.
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*
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* Copied from ARMv6 code, with the low level code inspired
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* by the ARMv7 Oprofile code.
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*
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* Cortex-A8 has up to 4 configurable performance counters and
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* a single cycle counter.
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* Cortex-A9 has up to 31 configurable performance counters and
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* a single cycle counter.
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*
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* All counters can be enabled/disabled and IRQ masked separately. The cycle
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* counter and all 4 performance counters together can be reset separately.
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*/
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#ifdef CONFIG_CPU_V7
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/irq_regs.h>
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#include <asm/vfp.h>
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#include "../vfp/vfpinstr.h"
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#include <linux/of.h>
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#include <linux/perf/arm_pmu.h>
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#include <linux/platform_device.h>
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/*
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* Common ARMv7 event types
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*
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* Note: An implementation may not be able to count all of these events
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* but the encodings are considered to be `reserved' in the case that
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* they are not available.
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*/
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#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
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#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
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#define ARMV7_PERFCTR_ITLB_REFILL 0x02
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#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
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#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
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#define ARMV7_PERFCTR_DTLB_REFILL 0x05
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#define ARMV7_PERFCTR_MEM_READ 0x06
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#define ARMV7_PERFCTR_MEM_WRITE 0x07
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#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
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#define ARMV7_PERFCTR_EXC_TAKEN 0x09
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#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
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#define ARMV7_PERFCTR_CID_WRITE 0x0B
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/*
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* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
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* It counts:
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* - all (taken) branch instructions,
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* - instructions that explicitly write the PC,
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* - exception generating instructions.
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*/
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#define ARMV7_PERFCTR_PC_WRITE 0x0C
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#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
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#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
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#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
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#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
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#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
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#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
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/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
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#define ARMV7_PERFCTR_MEM_ACCESS 0x13
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#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
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#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
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#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
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#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
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#define ARMV7_PERFCTR_L2_CACHE_WB 0x18
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#define ARMV7_PERFCTR_BUS_ACCESS 0x19
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#define ARMV7_PERFCTR_MEM_ERROR 0x1A
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#define ARMV7_PERFCTR_INSTR_SPEC 0x1B
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#define ARMV7_PERFCTR_TTBR_WRITE 0x1C
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#define ARMV7_PERFCTR_BUS_CYCLES 0x1D
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#define ARMV7_PERFCTR_CPU_CYCLES 0xFF
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/* ARMv7 Cortex-A8 specific event types */
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#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
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#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
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#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
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#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
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/* ARMv7 Cortex-A9 specific event types */
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#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
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#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
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#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
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/* ARMv7 Cortex-A5 specific event types */
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
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#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
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/* ARMv7 Cortex-A15 specific event types */
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
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#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
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#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
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#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
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#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
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/* ARMv7 Cortex-A12 specific event types */
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
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#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
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#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
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#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
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#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
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/* ARMv7 Krait specific event types */
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#define KRAIT_PMRESR0_GROUP0 0xcc
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#define KRAIT_PMRESR1_GROUP0 0xd0
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#define KRAIT_PMRESR2_GROUP0 0xd4
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#define KRAIT_VPMRESR0_GROUP0 0xd8
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#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
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#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
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#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
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#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
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/* ARMv7 Scorpion specific event types */
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#define SCORPION_LPM0_GROUP0 0x4c
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#define SCORPION_LPM1_GROUP0 0x50
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#define SCORPION_LPM2_GROUP0 0x54
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#define SCORPION_L2LPM_GROUP0 0x58
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#define SCORPION_VLPM_GROUP0 0x5c
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#define SCORPION_ICACHE_ACCESS 0x10053
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#define SCORPION_ICACHE_MISS 0x10052
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#define SCORPION_DTLB_ACCESS 0x12013
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#define SCORPION_DTLB_MISS 0x12012
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#define SCORPION_ITLB_MISS 0x12021
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/*
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* Cortex-A8 HW events mapping
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*
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* The hardware events that we support. We do support cache operations but
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* we have harvard caches and no way to combine instruction and data
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* accesses/misses in hardware.
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*/
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static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
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};
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static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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PERF_CACHE_MAP_ALL_UNSUPPORTED,
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/*
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* The performance counters don't differentiate between read and write
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* accesses/misses so this isn't strictly correct, but it's the best we
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* can do. Writes and reads get combined.
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*/
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[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
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[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
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[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
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[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
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[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
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[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
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[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
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[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
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[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
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[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
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[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
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[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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};
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/*
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* Cortex-A9 HW events mapping
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*/
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static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
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[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
|
|
};
|
|
|
|
static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
/*
|
|
* The performance counters don't differentiate between read and write
|
|
* accesses/misses so this isn't strictly correct, but it's the best we
|
|
* can do. Writes and reads get combined.
|
|
*/
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Cortex-A5 HW events mapping
|
|
*/
|
|
static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
|
|
[C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
|
|
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
/*
|
|
* The prefetch counters don't differentiate between the I side and the
|
|
* D side.
|
|
*/
|
|
[C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
|
|
[C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Cortex-A15 HW events mapping
|
|
*/
|
|
static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
|
|
};
|
|
|
|
static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
|
|
|
|
/*
|
|
* Not all performance counters differentiate between read and write
|
|
* accesses/misses so we're not always strictly correct, but it's the
|
|
* best we can do. Writes and reads get combined in these cases.
|
|
*/
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
|
|
[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
|
|
[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Cortex-A7 HW events mapping
|
|
*/
|
|
static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
|
|
};
|
|
|
|
static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
/*
|
|
* The performance counters don't differentiate between read and write
|
|
* accesses/misses so this isn't strictly correct, but it's the best we
|
|
* can do. Writes and reads get combined.
|
|
*/
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
|
|
[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
|
|
[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Cortex-A12 HW events mapping
|
|
*/
|
|
static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
|
|
};
|
|
|
|
static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
|
|
/*
|
|
* Not all performance counters differentiate between read and write
|
|
* accesses/misses so we're not always strictly correct, but it's the
|
|
* best we can do. Writes and reads get combined in these cases.
|
|
*/
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
|
|
|
[C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,
|
|
[C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,
|
|
[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
|
|
[C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Krait HW events mapping
|
|
*/
|
|
static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
|
};
|
|
|
|
static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
|
};
|
|
|
|
static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
|
|
/*
|
|
* The performance counters don't differentiate between read and write
|
|
* accesses/misses so this isn't strictly correct, but it's the best we
|
|
* can do. Writes and reads get combined.
|
|
*/
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS,
|
|
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
|
|
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
|
|
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
/*
|
|
* Scorpion HW events mapping
|
|
*/
|
|
static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
|
|
PERF_MAP_ALL_UNSUPPORTED,
|
|
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
|
};
|
|
|
|
static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
|
|
PERF_CACHE_MAP_ALL_UNSUPPORTED,
|
|
/*
|
|
* The performance counters don't differentiate between read and write
|
|
* accesses/misses so this isn't strictly correct, but it's the best we
|
|
* can do. Writes and reads get combined.
|
|
*/
|
|
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
|
|
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
|
|
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
|
|
/*
|
|
* Only ITLB misses and DTLB refills are supported. If users want the
|
|
* DTLB refills misses a raw counter must be used.
|
|
*/
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
|
|
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
|
|
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
|
|
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
|
|
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
|
|
[C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
|
};
|
|
|
|
PMU_FORMAT_ATTR(event, "config:0-7");
|
|
|
|
static struct attribute *armv7_pmu_format_attrs[] = {
|
|
&format_attr_event.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group armv7_pmu_format_attr_group = {
|
|
.name = "format",
|
|
.attrs = armv7_pmu_format_attrs,
|
|
};
|
|
|
|
#define ARMV7_EVENT_ATTR_RESOLVE(m) #m
|
|
#define ARMV7_EVENT_ATTR(name, config) \
|
|
PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \
|
|
"event=" ARMV7_EVENT_ATTR_RESOLVE(config))
|
|
|
|
ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR);
|
|
ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL);
|
|
ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL);
|
|
ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL);
|
|
ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS);
|
|
ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL);
|
|
ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ);
|
|
ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE);
|
|
ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED);
|
|
ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN);
|
|
ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED);
|
|
ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE);
|
|
ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE);
|
|
ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH);
|
|
ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN);
|
|
ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS);
|
|
ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED);
|
|
ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES);
|
|
ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED);
|
|
|
|
static struct attribute *armv7_pmuv1_event_attrs[] = {
|
|
&armv7_event_attr_sw_incr.attr.attr,
|
|
&armv7_event_attr_l1i_cache_refill.attr.attr,
|
|
&armv7_event_attr_l1i_tlb_refill.attr.attr,
|
|
&armv7_event_attr_l1d_cache_refill.attr.attr,
|
|
&armv7_event_attr_l1d_cache.attr.attr,
|
|
&armv7_event_attr_l1d_tlb_refill.attr.attr,
|
|
&armv7_event_attr_ld_retired.attr.attr,
|
|
&armv7_event_attr_st_retired.attr.attr,
|
|
&armv7_event_attr_inst_retired.attr.attr,
|
|
&armv7_event_attr_exc_taken.attr.attr,
|
|
&armv7_event_attr_exc_return.attr.attr,
|
|
&armv7_event_attr_cid_write_retired.attr.attr,
|
|
&armv7_event_attr_pc_write_retired.attr.attr,
|
|
&armv7_event_attr_br_immed_retired.attr.attr,
|
|
&armv7_event_attr_br_return_retired.attr.attr,
|
|
&armv7_event_attr_unaligned_ldst_retired.attr.attr,
|
|
&armv7_event_attr_br_mis_pred.attr.attr,
|
|
&armv7_event_attr_cpu_cycles.attr.attr,
|
|
&armv7_event_attr_br_pred.attr.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group armv7_pmuv1_events_attr_group = {
|
|
.name = "events",
|
|
.attrs = armv7_pmuv1_event_attrs,
|
|
};
|
|
|
|
ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS);
|
|
ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS);
|
|
ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB);
|
|
ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS);
|
|
ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL);
|
|
ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB);
|
|
ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS);
|
|
ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR);
|
|
ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC);
|
|
ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE);
|
|
ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES);
|
|
|
|
static struct attribute *armv7_pmuv2_event_attrs[] = {
|
|
&armv7_event_attr_sw_incr.attr.attr,
|
|
&armv7_event_attr_l1i_cache_refill.attr.attr,
|
|
&armv7_event_attr_l1i_tlb_refill.attr.attr,
|
|
&armv7_event_attr_l1d_cache_refill.attr.attr,
|
|
&armv7_event_attr_l1d_cache.attr.attr,
|
|
&armv7_event_attr_l1d_tlb_refill.attr.attr,
|
|
&armv7_event_attr_ld_retired.attr.attr,
|
|
&armv7_event_attr_st_retired.attr.attr,
|
|
&armv7_event_attr_inst_retired.attr.attr,
|
|
&armv7_event_attr_exc_taken.attr.attr,
|
|
&armv7_event_attr_exc_return.attr.attr,
|
|
&armv7_event_attr_cid_write_retired.attr.attr,
|
|
&armv7_event_attr_pc_write_retired.attr.attr,
|
|
&armv7_event_attr_br_immed_retired.attr.attr,
|
|
&armv7_event_attr_br_return_retired.attr.attr,
|
|
&armv7_event_attr_unaligned_ldst_retired.attr.attr,
|
|
&armv7_event_attr_br_mis_pred.attr.attr,
|
|
&armv7_event_attr_cpu_cycles.attr.attr,
|
|
&armv7_event_attr_br_pred.attr.attr,
|
|
&armv7_event_attr_mem_access.attr.attr,
|
|
&armv7_event_attr_l1i_cache.attr.attr,
|
|
&armv7_event_attr_l1d_cache_wb.attr.attr,
|
|
&armv7_event_attr_l2d_cache.attr.attr,
|
|
&armv7_event_attr_l2d_cache_refill.attr.attr,
|
|
&armv7_event_attr_l2d_cache_wb.attr.attr,
|
|
&armv7_event_attr_bus_access.attr.attr,
|
|
&armv7_event_attr_memory_error.attr.attr,
|
|
&armv7_event_attr_inst_spec.attr.attr,
|
|
&armv7_event_attr_ttbr_write_retired.attr.attr,
|
|
&armv7_event_attr_bus_cycles.attr.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group armv7_pmuv2_events_attr_group = {
|
|
.name = "events",
|
|
.attrs = armv7_pmuv2_event_attrs,
|
|
};
|
|
|
|
/*
|
|
* Perf Events' indices
|
|
*/
|
|
#define ARMV7_IDX_CYCLE_COUNTER 0
|
|
#define ARMV7_IDX_COUNTER0 1
|
|
#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \
|
|
(ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
|
|
|
|
#define ARMV7_MAX_COUNTERS 32
|
|
#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
|
|
|
|
/*
|
|
* ARMv7 low level PMNC access
|
|
*/
|
|
|
|
/*
|
|
* Perf Event to low level counters mapping
|
|
*/
|
|
#define ARMV7_IDX_TO_COUNTER(x) \
|
|
(((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
|
|
|
|
/*
|
|
* Per-CPU PMNC: config reg
|
|
*/
|
|
#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
|
|
#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
|
|
#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
|
|
#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
|
#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
|
|
#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
|
#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
|
|
#define ARMV7_PMNC_N_MASK 0x1f
|
|
#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
|
|
|
|
/*
|
|
* FLAG: counters overflow flag status reg
|
|
*/
|
|
#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
|
|
#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
|
|
|
|
/*
|
|
* PMXEVTYPER: Event selection reg
|
|
*/
|
|
#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
|
|
#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
|
|
|
|
/*
|
|
* Event filters for PMUv2
|
|
*/
|
|
#define ARMV7_EXCLUDE_PL1 (1 << 31)
|
|
#define ARMV7_EXCLUDE_USER (1 << 30)
|
|
#define ARMV7_INCLUDE_HYP (1 << 27)
|
|
|
|
/*
|
|
* Secure debug enable reg
|
|
*/
|
|
#define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */
|
|
|
|
static inline u32 armv7_pmnc_read(void)
|
|
{
|
|
u32 val;
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
|
|
return val;
|
|
}
|
|
|
|
static inline void armv7_pmnc_write(u32 val)
|
|
{
|
|
val &= ARMV7_PMNC_MASK;
|
|
isb();
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
|
|
}
|
|
|
|
static inline int armv7_pmnc_has_overflowed(u32 pmnc)
|
|
{
|
|
return pmnc & ARMV7_OVERFLOWED_MASK;
|
|
}
|
|
|
|
static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx)
|
|
{
|
|
return idx >= ARMV7_IDX_CYCLE_COUNTER &&
|
|
idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu);
|
|
}
|
|
|
|
static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
|
|
{
|
|
return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx));
|
|
}
|
|
|
|
static inline void armv7_pmnc_select_counter(int idx)
|
|
{
|
|
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
|
|
isb();
|
|
}
|
|
|
|
static inline u64 armv7pmu_read_counter(struct perf_event *event)
|
|
{
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
u32 value = 0;
|
|
|
|
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
|
pr_err("CPU%u reading wrong counter %d\n",
|
|
smp_processor_id(), idx);
|
|
} else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
|
|
} else {
|
|
armv7_pmnc_select_counter(idx);
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
static inline void armv7pmu_write_counter(struct perf_event *event, u64 value)
|
|
{
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
|
|
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
|
pr_err("CPU%u writing wrong counter %d\n",
|
|
smp_processor_id(), idx);
|
|
} else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value));
|
|
} else {
|
|
armv7_pmnc_select_counter(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value));
|
|
}
|
|
}
|
|
|
|
static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
|
|
{
|
|
armv7_pmnc_select_counter(idx);
|
|
val &= ARMV7_EVTYPE_MASK;
|
|
asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
|
|
}
|
|
|
|
static inline void armv7_pmnc_enable_counter(int idx)
|
|
{
|
|
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
|
|
}
|
|
|
|
static inline void armv7_pmnc_disable_counter(int idx)
|
|
{
|
|
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
|
|
}
|
|
|
|
static inline void armv7_pmnc_enable_intens(int idx)
|
|
{
|
|
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
|
|
}
|
|
|
|
static inline void armv7_pmnc_disable_intens(int idx)
|
|
{
|
|
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
|
|
isb();
|
|
/* Clear the overflow flag in case an interrupt is pending. */
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
|
|
isb();
|
|
}
|
|
|
|
static inline u32 armv7_pmnc_getreset_flags(void)
|
|
{
|
|
u32 val;
|
|
|
|
/* Read */
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
|
|
|
|
/* Write to clear flags */
|
|
val &= ARMV7_FLAG_MASK;
|
|
asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
|
|
|
|
return val;
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)
|
|
{
|
|
u32 val;
|
|
unsigned int cnt;
|
|
|
|
pr_info("PMNC registers dump:\n");
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
|
|
pr_info("PMNC =0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
|
|
pr_info("CNTENS=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
|
|
pr_info("INTENS=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
|
|
pr_info("FLAGS =0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
|
|
pr_info("SELECT=0x%08x\n", val);
|
|
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
|
|
pr_info("CCNT =0x%08x\n", val);
|
|
|
|
for (cnt = ARMV7_IDX_COUNTER0;
|
|
cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
|
|
armv7_pmnc_select_counter(cnt);
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
|
|
pr_info("CNT[%d] count =0x%08x\n",
|
|
ARMV7_IDX_TO_COUNTER(cnt), val);
|
|
asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
|
|
pr_info("CNT[%d] evtsel=0x%08x\n",
|
|
ARMV7_IDX_TO_COUNTER(cnt), val);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void armv7pmu_enable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
int idx = hwc->idx;
|
|
|
|
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
|
pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
|
|
smp_processor_id(), idx);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Enable counter and interrupt, and set the counter to count
|
|
* the event that we're interested in.
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/*
|
|
* Disable counter
|
|
*/
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Set event (if destined for PMNx counters)
|
|
* We only need to set the event for the cycle counter if we
|
|
* have the ability to perform event filtering.
|
|
*/
|
|
if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
|
|
armv7_pmnc_write_evtsel(idx, hwc->config_base);
|
|
|
|
/*
|
|
* Enable interrupt for this counter
|
|
*/
|
|
armv7_pmnc_enable_intens(idx);
|
|
|
|
/*
|
|
* Enable counter
|
|
*/
|
|
armv7_pmnc_enable_counter(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void armv7pmu_disable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
int idx = hwc->idx;
|
|
|
|
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
|
pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
|
|
smp_processor_id(), idx);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Disable counter and interrupt
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/*
|
|
* Disable counter
|
|
*/
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Disable interrupt for this counter
|
|
*/
|
|
armv7_pmnc_disable_intens(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu)
|
|
{
|
|
u32 pmnc;
|
|
struct perf_sample_data data;
|
|
struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
|
|
struct pt_regs *regs;
|
|
int idx;
|
|
|
|
/*
|
|
* Get and reset the IRQ flags
|
|
*/
|
|
pmnc = armv7_pmnc_getreset_flags();
|
|
|
|
/*
|
|
* Did an overflow occur?
|
|
*/
|
|
if (!armv7_pmnc_has_overflowed(pmnc))
|
|
return IRQ_NONE;
|
|
|
|
/*
|
|
* Handle the counter(s) overflow(s)
|
|
*/
|
|
regs = get_irq_regs();
|
|
|
|
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
|
struct perf_event *event = cpuc->events[idx];
|
|
struct hw_perf_event *hwc;
|
|
|
|
/* Ignore if we don't have an event. */
|
|
if (!event)
|
|
continue;
|
|
|
|
/*
|
|
* We have a single interrupt for all counters. Check that
|
|
* each counter has overflowed before we process it.
|
|
*/
|
|
if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
|
|
continue;
|
|
|
|
hwc = &event->hw;
|
|
armpmu_event_update(event);
|
|
perf_sample_data_init(&data, 0, hwc->last_period);
|
|
if (!armpmu_event_set_period(event))
|
|
continue;
|
|
|
|
if (perf_event_overflow(event, &data, regs))
|
|
cpu_pmu->disable(event);
|
|
}
|
|
|
|
/*
|
|
* Handle the pending perf events.
|
|
*
|
|
* Note: this call *must* be run with interrupts disabled. For
|
|
* platforms that can have the PMU interrupts raised as an NMI, this
|
|
* will not work.
|
|
*/
|
|
irq_work_run();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void armv7pmu_start(struct arm_pmu *cpu_pmu)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
/* Enable all counters */
|
|
armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void armv7pmu_stop(struct arm_pmu *cpu_pmu)
|
|
{
|
|
unsigned long flags;
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
/* Disable all counters */
|
|
armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
int idx;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;
|
|
|
|
/* Always place a cycle counter into the cycle counter. */
|
|
if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
|
|
if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))
|
|
return -EAGAIN;
|
|
|
|
return ARMV7_IDX_CYCLE_COUNTER;
|
|
}
|
|
|
|
/*
|
|
* For anything other than a cycle counter, try and use
|
|
* the events counters
|
|
*/
|
|
for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
|
|
if (!test_and_set_bit(idx, cpuc->used_mask))
|
|
return idx;
|
|
}
|
|
|
|
/* The counters are all in use. */
|
|
return -EAGAIN;
|
|
}
|
|
|
|
static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
clear_bit(event->hw.idx, cpuc->used_mask);
|
|
}
|
|
|
|
/*
|
|
* Add an event filter to a given event. This will only work for PMUv2 PMUs.
|
|
*/
|
|
static int armv7pmu_set_event_filter(struct hw_perf_event *event,
|
|
struct perf_event_attr *attr)
|
|
{
|
|
unsigned long config_base = 0;
|
|
|
|
if (attr->exclude_user)
|
|
config_base |= ARMV7_EXCLUDE_USER;
|
|
if (attr->exclude_kernel)
|
|
config_base |= ARMV7_EXCLUDE_PL1;
|
|
if (!attr->exclude_hv)
|
|
config_base |= ARMV7_INCLUDE_HYP;
|
|
|
|
/*
|
|
* Install the filter into config_base as this is used to
|
|
* construct the event type.
|
|
*/
|
|
event->config_base = config_base;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void armv7pmu_reset(void *info)
|
|
{
|
|
struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
|
|
u32 idx, nb_cnt = cpu_pmu->num_events, val;
|
|
|
|
if (cpu_pmu->secure_access) {
|
|
asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val));
|
|
val |= ARMV7_SDER_SUNIDEN;
|
|
asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val));
|
|
}
|
|
|
|
/* The counter and interrupt enable registers are unknown at reset. */
|
|
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
|
|
armv7_pmnc_disable_counter(idx);
|
|
armv7_pmnc_disable_intens(idx);
|
|
}
|
|
|
|
/* Initialize & Reset PMNC: C and P bits */
|
|
armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_P | ARMV7_PMNC_C);
|
|
}
|
|
|
|
static int armv7_a8_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a8_perf_map,
|
|
&armv7_a8_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a9_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a9_perf_map,
|
|
&armv7_a9_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a5_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a5_perf_map,
|
|
&armv7_a5_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a15_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a15_perf_map,
|
|
&armv7_a15_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a7_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a7_perf_map,
|
|
&armv7_a7_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int armv7_a12_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &armv7_a12_perf_map,
|
|
&armv7_a12_perf_cache_map, 0xFF);
|
|
}
|
|
|
|
static int krait_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &krait_perf_map,
|
|
&krait_perf_cache_map, 0xFFFFF);
|
|
}
|
|
|
|
static int krait_map_event_no_branch(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &krait_perf_map_no_branch,
|
|
&krait_perf_cache_map, 0xFFFFF);
|
|
}
|
|
|
|
static int scorpion_map_event(struct perf_event *event)
|
|
{
|
|
return armpmu_map_event(event, &scorpion_perf_map,
|
|
&scorpion_perf_cache_map, 0xFFFFF);
|
|
}
|
|
|
|
static void armv7pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pmu->handle_irq = armv7pmu_handle_irq;
|
|
cpu_pmu->enable = armv7pmu_enable_event;
|
|
cpu_pmu->disable = armv7pmu_disable_event;
|
|
cpu_pmu->read_counter = armv7pmu_read_counter;
|
|
cpu_pmu->write_counter = armv7pmu_write_counter;
|
|
cpu_pmu->get_event_idx = armv7pmu_get_event_idx;
|
|
cpu_pmu->clear_event_idx = armv7pmu_clear_event_idx;
|
|
cpu_pmu->start = armv7pmu_start;
|
|
cpu_pmu->stop = armv7pmu_stop;
|
|
cpu_pmu->reset = armv7pmu_reset;
|
|
};
|
|
|
|
static void armv7_read_num_pmnc_events(void *info)
|
|
{
|
|
int *nb_cnt = info;
|
|
|
|
/* Read the nb of CNTx counters supported from PMNC */
|
|
*nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
|
|
|
|
/* Add the CPU cycles counter */
|
|
*nb_cnt += 1;
|
|
}
|
|
|
|
static void armv7_pmu_idle_update(struct arm_pmu *cpu_pmu)
|
|
{
|
|
struct pmu_hw_events *hw_events;
|
|
struct perf_event *event;
|
|
int idx;
|
|
|
|
if (!cpu_pmu)
|
|
return;
|
|
|
|
hw_events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
if (!hw_events)
|
|
return;
|
|
|
|
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
|
event = hw_events->events[idx];
|
|
|
|
if (!event || !event->attr.exclude_idle ||
|
|
event->state != PERF_EVENT_STATE_ACTIVE)
|
|
continue;
|
|
|
|
cpu_pmu->pmu.read(event);
|
|
}
|
|
}
|
|
|
|
struct armv7_pmu_idle_nb {
|
|
struct arm_pmu *cpu_pmu;
|
|
struct notifier_block perf_cpu_idle_nb;
|
|
};
|
|
|
|
static int armv7_pmu_idle_notifier(struct notifier_block *nb,
|
|
unsigned long action, void *data)
|
|
{
|
|
struct armv7_pmu_idle_nb *pmu_idle_nb = container_of(nb,
|
|
struct armv7_pmu_idle_nb, perf_cpu_idle_nb);
|
|
|
|
if (action == IDLE_START)
|
|
armv7_pmu_idle_update(pmu_idle_nb->cpu_pmu);
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int armv7_probe_pmu(struct arm_pmu *arm_pmu)
|
|
{
|
|
int ret;
|
|
struct armv7_pmu_idle_nb *pmu_idle_nb;
|
|
|
|
pmu_idle_nb = devm_kzalloc(&arm_pmu->plat_device->dev,
|
|
sizeof(*pmu_idle_nb), GFP_KERNEL);
|
|
if (!pmu_idle_nb)
|
|
return -ENOMEM;
|
|
|
|
ret = smp_call_function_any(&arm_pmu->supported_cpus,
|
|
armv7_read_num_pmnc_events,
|
|
&arm_pmu->num_events, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pmu_idle_nb->cpu_pmu = arm_pmu;
|
|
pmu_idle_nb->perf_cpu_idle_nb.notifier_call = armv7_pmu_idle_notifier;
|
|
idle_notifier_register(&pmu_idle_nb->perf_cpu_idle_nb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a8";
|
|
cpu_pmu->map_event = armv7_a8_map_event;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv1_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a9";
|
|
cpu_pmu->map_event = armv7_a9_map_event;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv1_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a5";
|
|
cpu_pmu->map_event = armv7_a5_map_event;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv1_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a15";
|
|
cpu_pmu->map_event = armv7_a15_map_event;
|
|
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv2_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv8_pmuv3_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_pmuv3";
|
|
cpu_pmu->map_event = armv7_a7_map_event;
|
|
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv2_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a7";
|
|
cpu_pmu->map_event = armv7_a7_map_event;
|
|
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv2_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a12";
|
|
cpu_pmu->map_event = armv7_a12_map_event;
|
|
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv2_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
int ret = armv7_a12_pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_cortex_a17";
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
|
|
&armv7_pmuv2_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
|
|
&armv7_pmu_format_attr_group;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Krait Performance Monitor Region Event Selection Register (PMRESRn)
|
|
*
|
|
* 31 30 24 16 8 0
|
|
* +--------------------------------+
|
|
* PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
|
|
* +--------------------------------+
|
|
* PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1
|
|
* +--------------------------------+
|
|
* PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2
|
|
* +--------------------------------+
|
|
* VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ?
|
|
* +--------------------------------+
|
|
* EN | G=3 | G=2 | G=1 | G=0
|
|
*
|
|
* Event Encoding:
|
|
*
|
|
* hwc->config_base = 0xNRCCG
|
|
*
|
|
* N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
|
|
* R = region register
|
|
* CC = class of events the group G is choosing from
|
|
* G = group or particular event
|
|
*
|
|
* Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
|
|
*
|
|
* A region (R) corresponds to a piece of the CPU (execution unit, instruction
|
|
* unit, etc.) while the event code (CC) corresponds to a particular class of
|
|
* events (interrupts for example). An event code is broken down into
|
|
* groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
|
|
* example).
|
|
*/
|
|
|
|
#define KRAIT_EVENT (1 << 16)
|
|
#define VENUM_EVENT (2 << 16)
|
|
#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT)
|
|
#define PMRESRn_EN BIT(31)
|
|
|
|
#define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */
|
|
#define EVENT_GROUP(event) ((event) & 0xf) /* G */
|
|
#define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */
|
|
#define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */
|
|
#define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */
|
|
|
|
static u32 krait_read_pmresrn(int n)
|
|
{
|
|
u32 val;
|
|
|
|
switch (n) {
|
|
case 0:
|
|
asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));
|
|
break;
|
|
case 1:
|
|
asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));
|
|
break;
|
|
case 2:
|
|
asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));
|
|
break;
|
|
default:
|
|
BUG(); /* Should be validated in krait_pmu_get_event_idx() */
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void krait_write_pmresrn(int n, u32 val)
|
|
{
|
|
switch (n) {
|
|
case 0:
|
|
asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));
|
|
break;
|
|
case 1:
|
|
asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));
|
|
break;
|
|
case 2:
|
|
asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));
|
|
break;
|
|
default:
|
|
BUG(); /* Should be validated in krait_pmu_get_event_idx() */
|
|
}
|
|
}
|
|
|
|
static u32 venum_read_pmresr(void)
|
|
{
|
|
u32 val;
|
|
asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));
|
|
return val;
|
|
}
|
|
|
|
static void venum_write_pmresr(u32 val)
|
|
{
|
|
asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));
|
|
}
|
|
|
|
static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val)
|
|
{
|
|
u32 venum_new_val;
|
|
u32 fp_new_val;
|
|
|
|
BUG_ON(preemptible());
|
|
/* CPACR Enable CP10 and CP11 access */
|
|
*venum_orig_val = get_copro_access();
|
|
venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11);
|
|
set_copro_access(venum_new_val);
|
|
|
|
/* Enable FPEXC */
|
|
*fp_orig_val = fmrx(FPEXC);
|
|
fp_new_val = *fp_orig_val | FPEXC_EN;
|
|
fmxr(FPEXC, fp_new_val);
|
|
}
|
|
|
|
static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val)
|
|
{
|
|
BUG_ON(preemptible());
|
|
/* Restore FPEXC */
|
|
fmxr(FPEXC, fp_orig_val);
|
|
isb();
|
|
/* Restore CPACR */
|
|
set_copro_access(venum_orig_val);
|
|
}
|
|
|
|
static u32 krait_get_pmresrn_event(unsigned int region)
|
|
{
|
|
static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0,
|
|
KRAIT_PMRESR1_GROUP0,
|
|
KRAIT_PMRESR2_GROUP0 };
|
|
return pmresrn_table[region];
|
|
}
|
|
|
|
static void krait_evt_setup(int idx, u32 config_base)
|
|
{
|
|
u32 val;
|
|
u32 mask;
|
|
u32 vval, fval;
|
|
unsigned int region = EVENT_REGION(config_base);
|
|
unsigned int group = EVENT_GROUP(config_base);
|
|
unsigned int code = EVENT_CODE(config_base);
|
|
unsigned int group_shift;
|
|
bool venum_event = EVENT_VENUM(config_base);
|
|
|
|
group_shift = group * 8;
|
|
mask = 0xff << group_shift;
|
|
|
|
/* Configure evtsel for the region and group */
|
|
if (venum_event)
|
|
val = KRAIT_VPMRESR0_GROUP0;
|
|
else
|
|
val = krait_get_pmresrn_event(region);
|
|
val += group;
|
|
/* Mix in mode-exclusion bits */
|
|
val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1);
|
|
armv7_pmnc_write_evtsel(idx, val);
|
|
|
|
if (venum_event) {
|
|
venum_pre_pmresr(&vval, &fval);
|
|
val = venum_read_pmresr();
|
|
val &= ~mask;
|
|
val |= code << group_shift;
|
|
val |= PMRESRn_EN;
|
|
venum_write_pmresr(val);
|
|
venum_post_pmresr(vval, fval);
|
|
} else {
|
|
val = krait_read_pmresrn(region);
|
|
val &= ~mask;
|
|
val |= code << group_shift;
|
|
val |= PMRESRn_EN;
|
|
krait_write_pmresrn(region, val);
|
|
}
|
|
}
|
|
|
|
static u32 clear_pmresrn_group(u32 val, int group)
|
|
{
|
|
u32 mask;
|
|
int group_shift;
|
|
|
|
group_shift = group * 8;
|
|
mask = 0xff << group_shift;
|
|
val &= ~mask;
|
|
|
|
/* Don't clear enable bit if entire region isn't disabled */
|
|
if (val & ~PMRESRn_EN)
|
|
return val |= PMRESRn_EN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void krait_clearpmu(u32 config_base)
|
|
{
|
|
u32 val;
|
|
u32 vval, fval;
|
|
unsigned int region = EVENT_REGION(config_base);
|
|
unsigned int group = EVENT_GROUP(config_base);
|
|
bool venum_event = EVENT_VENUM(config_base);
|
|
|
|
if (venum_event) {
|
|
venum_pre_pmresr(&vval, &fval);
|
|
val = venum_read_pmresr();
|
|
val = clear_pmresrn_group(val, group);
|
|
venum_write_pmresr(val);
|
|
venum_post_pmresr(vval, fval);
|
|
} else {
|
|
val = krait_read_pmresrn(region);
|
|
val = clear_pmresrn_group(val, group);
|
|
krait_write_pmresrn(region, val);
|
|
}
|
|
}
|
|
|
|
static void krait_pmu_disable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
/* Disable counter and interrupt */
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/* Disable counter */
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Clear pmresr code (if destined for PMNx counters)
|
|
*/
|
|
if (hwc->config_base & KRAIT_EVENT_MASK)
|
|
krait_clearpmu(hwc->config_base);
|
|
|
|
/* Disable interrupt for this counter */
|
|
armv7_pmnc_disable_intens(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void krait_pmu_enable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
/*
|
|
* Enable counter and interrupt, and set the counter to count
|
|
* the event that we're interested in.
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/* Disable counter */
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Set event (if destined for PMNx counters)
|
|
* We set the event for the cycle counter because we
|
|
* have the ability to perform event filtering.
|
|
*/
|
|
if (hwc->config_base & KRAIT_EVENT_MASK)
|
|
krait_evt_setup(idx, hwc->config_base);
|
|
else
|
|
armv7_pmnc_write_evtsel(idx, hwc->config_base);
|
|
|
|
/* Enable interrupt for this counter */
|
|
armv7_pmnc_enable_intens(idx);
|
|
|
|
/* Enable counter */
|
|
armv7_pmnc_enable_counter(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void krait_pmu_reset(void *info)
|
|
{
|
|
u32 vval, fval;
|
|
struct arm_pmu *cpu_pmu = info;
|
|
u32 idx, nb_cnt = cpu_pmu->num_events;
|
|
|
|
armv7pmu_reset(info);
|
|
|
|
/* Clear all pmresrs */
|
|
krait_write_pmresrn(0, 0);
|
|
krait_write_pmresrn(1, 0);
|
|
krait_write_pmresrn(2, 0);
|
|
|
|
venum_pre_pmresr(&vval, &fval);
|
|
venum_write_pmresr(0);
|
|
venum_post_pmresr(vval, fval);
|
|
|
|
/* Reset PMxEVNCTCR to sane default */
|
|
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
|
|
armv7_pmnc_select_counter(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
|
|
}
|
|
|
|
}
|
|
|
|
static int krait_event_to_bit(struct perf_event *event, unsigned int region,
|
|
unsigned int group)
|
|
{
|
|
int bit;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
|
|
if (hwc->config_base & VENUM_EVENT)
|
|
bit = KRAIT_VPMRESR0_GROUP0;
|
|
else
|
|
bit = krait_get_pmresrn_event(region);
|
|
bit -= krait_get_pmresrn_event(0);
|
|
bit += group;
|
|
/*
|
|
* Lower bits are reserved for use by the counters (see
|
|
* armv7pmu_get_event_idx() for more info)
|
|
*/
|
|
bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;
|
|
|
|
return bit;
|
|
}
|
|
|
|
/*
|
|
* We check for column exclusion constraints here.
|
|
* Two events cant use the same group within a pmresr register.
|
|
*/
|
|
static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
int idx;
|
|
int bit = -1;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int region = EVENT_REGION(hwc->config_base);
|
|
unsigned int code = EVENT_CODE(hwc->config_base);
|
|
unsigned int group = EVENT_GROUP(hwc->config_base);
|
|
bool venum_event = EVENT_VENUM(hwc->config_base);
|
|
bool krait_event = EVENT_CPU(hwc->config_base);
|
|
|
|
if (venum_event || krait_event) {
|
|
/* Ignore invalid events */
|
|
if (group > 3 || region > 2)
|
|
return -EINVAL;
|
|
if (venum_event && (code & 0xe0))
|
|
return -EINVAL;
|
|
|
|
bit = krait_event_to_bit(event, region, group);
|
|
if (test_and_set_bit(bit, cpuc->used_mask))
|
|
return -EAGAIN;
|
|
}
|
|
|
|
idx = armv7pmu_get_event_idx(cpuc, event);
|
|
if (idx < 0 && bit >= 0)
|
|
clear_bit(bit, cpuc->used_mask);
|
|
|
|
return idx;
|
|
}
|
|
|
|
static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
int bit;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int region = EVENT_REGION(hwc->config_base);
|
|
unsigned int group = EVENT_GROUP(hwc->config_base);
|
|
bool venum_event = EVENT_VENUM(hwc->config_base);
|
|
bool krait_event = EVENT_CPU(hwc->config_base);
|
|
|
|
armv7pmu_clear_event_idx(cpuc, event);
|
|
if (venum_event || krait_event) {
|
|
bit = krait_event_to_bit(event, region, group);
|
|
clear_bit(bit, cpuc->used_mask);
|
|
}
|
|
}
|
|
|
|
static int krait_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_krait";
|
|
/* Some early versions of Krait don't support PC write events */
|
|
if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node,
|
|
"qcom,no-pc-write"))
|
|
cpu_pmu->map_event = krait_map_event_no_branch;
|
|
else
|
|
cpu_pmu->map_event = krait_map_event;
|
|
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
|
cpu_pmu->reset = krait_pmu_reset;
|
|
cpu_pmu->enable = krait_pmu_enable_event;
|
|
cpu_pmu->disable = krait_pmu_disable_event;
|
|
cpu_pmu->get_event_idx = krait_pmu_get_event_idx;
|
|
cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
/*
|
|
* Scorpion Local Performance Monitor Register (LPMn)
|
|
*
|
|
* 31 30 24 16 8 0
|
|
* +--------------------------------+
|
|
* LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
|
|
* +--------------------------------+
|
|
* LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1
|
|
* +--------------------------------+
|
|
* LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2
|
|
* +--------------------------------+
|
|
* L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3
|
|
* +--------------------------------+
|
|
* VLPM | EN | CC | CC | CC | CC | N = 2, R = ?
|
|
* +--------------------------------+
|
|
* EN | G=3 | G=2 | G=1 | G=0
|
|
*
|
|
*
|
|
* Event Encoding:
|
|
*
|
|
* hwc->config_base = 0xNRCCG
|
|
*
|
|
* N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM)
|
|
* R = region register
|
|
* CC = class of events the group G is choosing from
|
|
* G = group or particular event
|
|
*
|
|
* Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
|
|
*
|
|
* A region (R) corresponds to a piece of the CPU (execution unit, instruction
|
|
* unit, etc.) while the event code (CC) corresponds to a particular class of
|
|
* events (interrupts for example). An event code is broken down into
|
|
* groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
|
|
* example).
|
|
*/
|
|
|
|
static u32 scorpion_read_pmresrn(int n)
|
|
{
|
|
u32 val;
|
|
|
|
switch (n) {
|
|
case 0:
|
|
asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val));
|
|
break;
|
|
case 1:
|
|
asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
|
|
break;
|
|
case 2:
|
|
asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val));
|
|
break;
|
|
case 3:
|
|
asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val));
|
|
break;
|
|
default:
|
|
BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void scorpion_write_pmresrn(int n, u32 val)
|
|
{
|
|
switch (n) {
|
|
case 0:
|
|
asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val));
|
|
break;
|
|
case 1:
|
|
asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));
|
|
break;
|
|
case 2:
|
|
asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val));
|
|
break;
|
|
case 3:
|
|
asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val));
|
|
break;
|
|
default:
|
|
BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
|
|
}
|
|
}
|
|
|
|
static u32 scorpion_get_pmresrn_event(unsigned int region)
|
|
{
|
|
static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0,
|
|
SCORPION_LPM1_GROUP0,
|
|
SCORPION_LPM2_GROUP0,
|
|
SCORPION_L2LPM_GROUP0 };
|
|
return pmresrn_table[region];
|
|
}
|
|
|
|
static void scorpion_evt_setup(int idx, u32 config_base)
|
|
{
|
|
u32 val;
|
|
u32 mask;
|
|
u32 vval, fval;
|
|
unsigned int region = EVENT_REGION(config_base);
|
|
unsigned int group = EVENT_GROUP(config_base);
|
|
unsigned int code = EVENT_CODE(config_base);
|
|
unsigned int group_shift;
|
|
bool venum_event = EVENT_VENUM(config_base);
|
|
|
|
group_shift = group * 8;
|
|
mask = 0xff << group_shift;
|
|
|
|
/* Configure evtsel for the region and group */
|
|
if (venum_event)
|
|
val = SCORPION_VLPM_GROUP0;
|
|
else
|
|
val = scorpion_get_pmresrn_event(region);
|
|
val += group;
|
|
/* Mix in mode-exclusion bits */
|
|
val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1);
|
|
armv7_pmnc_write_evtsel(idx, val);
|
|
|
|
asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
|
|
|
|
if (venum_event) {
|
|
venum_pre_pmresr(&vval, &fval);
|
|
val = venum_read_pmresr();
|
|
val &= ~mask;
|
|
val |= code << group_shift;
|
|
val |= PMRESRn_EN;
|
|
venum_write_pmresr(val);
|
|
venum_post_pmresr(vval, fval);
|
|
} else {
|
|
val = scorpion_read_pmresrn(region);
|
|
val &= ~mask;
|
|
val |= code << group_shift;
|
|
val |= PMRESRn_EN;
|
|
scorpion_write_pmresrn(region, val);
|
|
}
|
|
}
|
|
|
|
static void scorpion_clearpmu(u32 config_base)
|
|
{
|
|
u32 val;
|
|
u32 vval, fval;
|
|
unsigned int region = EVENT_REGION(config_base);
|
|
unsigned int group = EVENT_GROUP(config_base);
|
|
bool venum_event = EVENT_VENUM(config_base);
|
|
|
|
if (venum_event) {
|
|
venum_pre_pmresr(&vval, &fval);
|
|
val = venum_read_pmresr();
|
|
val = clear_pmresrn_group(val, group);
|
|
venum_write_pmresr(val);
|
|
venum_post_pmresr(vval, fval);
|
|
} else {
|
|
val = scorpion_read_pmresrn(region);
|
|
val = clear_pmresrn_group(val, group);
|
|
scorpion_write_pmresrn(region, val);
|
|
}
|
|
}
|
|
|
|
static void scorpion_pmu_disable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
/* Disable counter and interrupt */
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/* Disable counter */
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Clear pmresr code (if destined for PMNx counters)
|
|
*/
|
|
if (hwc->config_base & KRAIT_EVENT_MASK)
|
|
scorpion_clearpmu(hwc->config_base);
|
|
|
|
/* Disable interrupt for this counter */
|
|
armv7_pmnc_disable_intens(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void scorpion_pmu_enable_event(struct perf_event *event)
|
|
{
|
|
unsigned long flags;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
int idx = hwc->idx;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
|
|
|
|
/*
|
|
* Enable counter and interrupt, and set the counter to count
|
|
* the event that we're interested in.
|
|
*/
|
|
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
|
|
|
/* Disable counter */
|
|
armv7_pmnc_disable_counter(idx);
|
|
|
|
/*
|
|
* Set event (if destined for PMNx counters)
|
|
* We don't set the event for the cycle counter because we
|
|
* don't have the ability to perform event filtering.
|
|
*/
|
|
if (hwc->config_base & KRAIT_EVENT_MASK)
|
|
scorpion_evt_setup(idx, hwc->config_base);
|
|
else if (idx != ARMV7_IDX_CYCLE_COUNTER)
|
|
armv7_pmnc_write_evtsel(idx, hwc->config_base);
|
|
|
|
/* Enable interrupt for this counter */
|
|
armv7_pmnc_enable_intens(idx);
|
|
|
|
/* Enable counter */
|
|
armv7_pmnc_enable_counter(idx);
|
|
|
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
|
}
|
|
|
|
static void scorpion_pmu_reset(void *info)
|
|
{
|
|
u32 vval, fval;
|
|
struct arm_pmu *cpu_pmu = info;
|
|
u32 idx, nb_cnt = cpu_pmu->num_events;
|
|
|
|
armv7pmu_reset(info);
|
|
|
|
/* Clear all pmresrs */
|
|
scorpion_write_pmresrn(0, 0);
|
|
scorpion_write_pmresrn(1, 0);
|
|
scorpion_write_pmresrn(2, 0);
|
|
scorpion_write_pmresrn(3, 0);
|
|
|
|
venum_pre_pmresr(&vval, &fval);
|
|
venum_write_pmresr(0);
|
|
venum_post_pmresr(vval, fval);
|
|
|
|
/* Reset PMxEVNCTCR to sane default */
|
|
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
|
|
armv7_pmnc_select_counter(idx);
|
|
asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
|
|
}
|
|
}
|
|
|
|
static int scorpion_event_to_bit(struct perf_event *event, unsigned int region,
|
|
unsigned int group)
|
|
{
|
|
int bit;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
|
|
|
if (hwc->config_base & VENUM_EVENT)
|
|
bit = SCORPION_VLPM_GROUP0;
|
|
else
|
|
bit = scorpion_get_pmresrn_event(region);
|
|
bit -= scorpion_get_pmresrn_event(0);
|
|
bit += group;
|
|
/*
|
|
* Lower bits are reserved for use by the counters (see
|
|
* armv7pmu_get_event_idx() for more info)
|
|
*/
|
|
bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;
|
|
|
|
return bit;
|
|
}
|
|
|
|
/*
|
|
* We check for column exclusion constraints here.
|
|
* Two events cant use the same group within a pmresr register.
|
|
*/
|
|
static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
int idx;
|
|
int bit = -1;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int region = EVENT_REGION(hwc->config_base);
|
|
unsigned int group = EVENT_GROUP(hwc->config_base);
|
|
bool venum_event = EVENT_VENUM(hwc->config_base);
|
|
bool scorpion_event = EVENT_CPU(hwc->config_base);
|
|
|
|
if (venum_event || scorpion_event) {
|
|
/* Ignore invalid events */
|
|
if (group > 3 || region > 3)
|
|
return -EINVAL;
|
|
|
|
bit = scorpion_event_to_bit(event, region, group);
|
|
if (test_and_set_bit(bit, cpuc->used_mask))
|
|
return -EAGAIN;
|
|
}
|
|
|
|
idx = armv7pmu_get_event_idx(cpuc, event);
|
|
if (idx < 0 && bit >= 0)
|
|
clear_bit(bit, cpuc->used_mask);
|
|
|
|
return idx;
|
|
}
|
|
|
|
static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
int bit;
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int region = EVENT_REGION(hwc->config_base);
|
|
unsigned int group = EVENT_GROUP(hwc->config_base);
|
|
bool venum_event = EVENT_VENUM(hwc->config_base);
|
|
bool scorpion_event = EVENT_CPU(hwc->config_base);
|
|
|
|
armv7pmu_clear_event_idx(cpuc, event);
|
|
if (venum_event || scorpion_event) {
|
|
bit = scorpion_event_to_bit(event, region, group);
|
|
clear_bit(bit, cpuc->used_mask);
|
|
}
|
|
}
|
|
|
|
static int scorpion_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_scorpion";
|
|
cpu_pmu->map_event = scorpion_map_event;
|
|
cpu_pmu->reset = scorpion_pmu_reset;
|
|
cpu_pmu->enable = scorpion_pmu_enable_event;
|
|
cpu_pmu->disable = scorpion_pmu_disable_event;
|
|
cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx;
|
|
cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
armv7pmu_init(cpu_pmu);
|
|
cpu_pmu->name = "armv7_scorpion_mp";
|
|
cpu_pmu->map_event = scorpion_map_event;
|
|
cpu_pmu->reset = scorpion_pmu_reset;
|
|
cpu_pmu->enable = scorpion_pmu_enable_event;
|
|
cpu_pmu->disable = scorpion_pmu_disable_event;
|
|
cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx;
|
|
cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx;
|
|
return armv7_probe_pmu(cpu_pmu);
|
|
}
|
|
|
|
static const struct of_device_id armv7_pmu_of_device_ids[] = {
|
|
{.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init},
|
|
{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
|
|
{.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init},
|
|
{.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
|
|
{.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
|
|
{.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
|
|
{.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
|
|
{.compatible = "qcom,krait-pmu", .data = krait_pmu_init},
|
|
{.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
|
|
{.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init},
|
|
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
|
|
{},
|
|
};
|
|
|
|
static const struct pmu_probe_info armv7_pmu_probe_table[] = {
|
|
ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init),
|
|
ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init),
|
|
{ /* sentinel value */ }
|
|
};
|
|
|
|
|
|
static int armv7_pmu_device_probe(struct platform_device *pdev)
|
|
{
|
|
return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids,
|
|
armv7_pmu_probe_table);
|
|
}
|
|
|
|
static struct platform_driver armv7_pmu_driver = {
|
|
.driver = {
|
|
.name = "armv7-pmu",
|
|
.of_match_table = armv7_pmu_of_device_ids,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = armv7_pmu_device_probe,
|
|
};
|
|
|
|
builtin_platform_driver(armv7_pmu_driver);
|
|
#endif /* CONFIG_CPU_V7 */
|