Commit Graph

257 Commits

Author SHA1 Message Date
Linus Torvalds
d07b3c2532 Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
  [ARM] spelling fixes
  [ARM] at91_adc parenthesis balance
  [ARM] 4400/1: S3C24XX: Add high-speed MMC device definition
  [ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings
  [ARM] 4398/1: S3C2443: Fix watchdog IRQ number
  [ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity
  [ARM] 4396/1: S3C2443: Add missing HCLK clocks
  [ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines
  [ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu
  [ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts
  [ARM] ARMv6: add CPU_HAS_ASID configuration
  [ARM] integrator: fix pci_v3 compile error with DEBUG_LL
  [ARM] gic: Fix gic cascade irq handling
  [ARM] Silence OMAP kernel configuration warning
  [ARM] Update ARM syscalls
  [ARM] 4384/1: S3C2412/13 SPI registers offset correction
  [ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
  [ARM] 4382/1: iop13xx: fix msi support
  [ARM] Remove Integrator/CP SMP platform support
  [ARM] 4378/1: KS8695: Serial driver fix
  ...
2007-05-21 10:00:22 -07:00
Alexey Dobriyan
e8edc6e03a Detach sched.h from mm.h
First thing mm.h does is including sched.h solely for can_do_mlock() inline
function which has "current" dereference inside. By dealing with can_do_mlock()
mm.h can be detached from sched.h which is good. See below, why.

This patch
a) removes unconditional inclusion of sched.h from mm.h
b) makes can_do_mlock() normal function in mm/mlock.c
c) exports can_do_mlock() to not break compilation
d) adds sched.h inclusions back to files that were getting it indirectly.
e) adds less bloated headers to some files (asm/signal.h, jiffies.h) that were
   getting them indirectly

Net result is:
a) mm.h users would get less code to open, read, preprocess, parse, ... if
   they don't need sched.h
b) sched.h stops being dependency for significant number of files:
   on x86_64 allmodconfig touching sched.h results in recompile of 4083 files,
   after patch it's only 3744 (-8.3%).

Cross-compile tested on

	all arm defconfigs, all mips defconfigs, all powerpc defconfigs,
	alpha alpha-up
	arm
	i386 i386-up i386-defconfig i386-allnoconfig
	ia64 ia64-up
	m68k
	mips
	parisc parisc-up
	powerpc powerpc-up
	s390 s390-up
	sparc sparc-up
	sparc64 sparc64-up
	um-x86_64
	x86_64 x86_64-up x86_64-defconfig x86_64-allnoconfig

as well as my two usual configs.

Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-21 09:18:19 -07:00
Simon Arlott
6cbdc8c535 [ARM] spelling fixes
Spelling fixes in arch/arm/.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-20 20:10:32 +01:00
Russell King
516793c61b [ARM] ARMv6: add CPU_HAS_ASID configuration
Presently, we check for the minimum ARM architecture that we're
building for to determine whether we need ASID support.  This is
wrong - if we're going to support a range of CPUs which include
ARMv6 or higher, we need the ASID.

Convert the checks to use a new configuration symbol, and arrange
for ARMv6 and higher CPU entries to select it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-17 10:19:23 +01:00
Andrew Victor
c53c9cf60e [ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
Add core support for the Kendin/Micrel KS8695 processor family.

It is an ARM922-T based SoC with integrated USART, 4-port Ethernet
Switch, WAN Ethernet port, and optional PCI Host bridge, etc.
 http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp

This patch is based on earlier patches from Lennert Buytenhek, Ben
Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in
March 2006;  and Micrel's 2.6.9 port.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 22:02:48 +01:00
Andrew Victor
877d7720f5 [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
Add support for Atmel's new AT91SAM9RL range of processors.
Includes similar peripherals as other AT91SAM9 processors, but with a
High-speed USB controller and various sizes of internal SRAM.

Signed-off-by: Nicolas Ferre <nicolas.ferre@rfo.atmel.com>
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 21:07:54 +01:00
Kevin Hilman
7c6337e225 [ARM] 4303/3: base kernel support for TI DaVinci
Add base kernel support for the TI DaVinci platform.

This patch only includes interrupts, timers, CPU identification,
serial support and basic power and sleep controller init.  More
drivers to come.

Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-11 17:26:55 +01:00
Linus Torvalds
932c37c375 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
  ARM: OMAP: Fix GCC-reported compile time bug
  ARM: OMAP: restore CONFIG_GENERIC_TIME
  ARM: OMAP: partial LED fixes
  ARM: OMAP: add SoSSI clock (call propagate_rate for childrens)
  ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations)
  ARM: OMAP: Sync framebuffer headers with N800 tree
  ARM: OMAP: Mostly cosmetic to sync up with linux-omap tree
  ARM: OMAP: Fix gpmc header
  ARM: OMAP: Add mailbox support for IVA
  [ARM] armv7: add Makefile and Kconfig entries
  [ARM] armv7: add support for asid-tagged VIVT I-cache
  [ARM] armv7: add dedicated ARMv7 barrier instructions
  [ARM] armv7: Add ARMv7 cacheid macros
  [ARM] armv7: add support for ARMv7 cores.
  [ARM] Fix ARM branch relocation range
  [ARM] 4363/1: AT91: Remove legacy PIO definitions
  [ARM] 4361/1: AT91: Build error
  ARM: OMAP: Sync core code with linux-omap
  ARM: OMAP: Sync headers with linux-omap
  ARM: OMAP: h4 must have blinky leds!!
  ...
2007-05-09 13:05:57 -07:00
Russell King
805f53f085 Merge branches 'armv7', 'at91', 'misc' and 'omap' into devel 2007-05-09 10:41:28 +01:00
Catalin Marinas
23688e999e [ARM] armv7: add Makefile and Kconfig entries
This patch adds the necessary lines to the Makefile and Kconfig files for
enabling the compilation of the ARMv7 CPU support.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-09 09:52:38 +01:00
Catalin Marinas
065cf519c3 [ARM] armv7: add support for asid-tagged VIVT I-cache
ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch
adds the necessary invalidation of the I-cache when the ASID numbers
are re-used.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-09 09:50:23 +01:00
Catalin Marinas
bbe888864e [ARM] armv7: add support for ARMv7 cores.
This patch adds support for the ARMv7 cores.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-08 22:55:53 +01:00
Russell King
8678c1f042 [ARM] Fix ASID version switch
Close a hole in the ASID version switch, particularly the following
scenario:

CPU0 MM PID			CPU1 MM PID
	idle
				  A	pid(A)
				  A	idle(lazy tlb)
		* new asid version triggered by B *
  B	pid(B)
  A	pid(A)
		* MM A gets new asid version *
  A	idle(lazy tlb)
				  A	pid(A)
		* CPU1 doesn't see the new ASID *

The result is that CPU1 continues running with the hardware set
for the original (stale) ASID value, but mm->context.id contains
the new ASID value.  The result is that the next MM fault on CPU1
updates the page table entries, but flush_tlb_page() fails due to
wrong ASID.

There is a related case with a threaded application is allocated
a new ASID on one CPU while another of its threads is running on
some different CPU.  This scenario is not fixed by this commit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-08 20:03:09 +01:00
Christoph Hellwig
1eeb66a1bb move die notifier handling to common code
This patch moves the die notifier handling to common code.  Previous
various architectures had exactly the same code for it.  Note that the new
code is compiled unconditionally, this should be understood as an appel to
the other architecture maintainer to implement support for it aswell (aka
sprinkling a notify_die or two in the proper place)

arm had a notifiy_die that did something totally different, I renamed it to
arm_notify_die as part of the patch and made it static to the file it's
declared and used at.  avr32 used to pass slightly less information through
this interface and I brought it into line with the other architectures.

[akpm@linux-foundation.org: build fix]
[akpm@linux-foundation.org: fix vmalloc_sync_all bustage]
[bryan.wu@analog.com: fix vmalloc_sync_all in nommu]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Cc: <linux-arch@vger.kernel.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-08 11:15:04 -07:00
Benjamin Herrenschmidt
acec0ac0a8 get_unmapped_area handles MAP_FIXED on arm
ARM already had a case for MAP_FIXED in arch_get_unmapped_area() though it was
not called before.  Fix the comment to reflect that it will now be called.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 12:12:56 -07:00
Russell King
5cd4715515 Merge branch 'ixp4xx' into devel
Conflicts:

	include/asm-arm/arch-ixp4xx/io.h
2007-05-06 20:58:29 +01:00
Russell King
3603ab2b62 [ARM] mm 10: allow memory type to be specified with ioremap
__ioremap() took a set of page table flags (specifically the cacheable
and bufferable bits) to control the mapping type.  However, with
the advent of ARMv6, this is far too limited.

Replace the page table flags with a memory type index, so that the
desired attributes can be selected from the mem_type table.

Finally, to prevent silent miscompilation due to the differing
arguments, rename the __ioremap() and __ioremap_pfn() functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-05 20:59:27 +01:00
Russell King
0af92befeb [ARM] mm 9: add additional device memory types
Add cached device type for ioremap_cached().  Group all device memory
types together, and ensure that they all have a "MT_DEVICE" prefix.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-05 20:28:16 +01:00
Russell King
9ef7963503 [ARM] mm 8: define mem_types table L1 bit 4 to be for ARMv6
Change the memory types table to define the L1 descriptor bit 4 to
be in terms of the ARMv6 definition - execute never.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-05-05 20:03:35 +01:00
Ruslan V. Sushko
45fba0846f [ARM] 4311/1: ixp4xx: add KIXRP435 platform
Add Intel KIXRP435 Reference Platform based on IXP43x processor.
Fixed after review : access to cp15 removed in identification functions,
used access to global processor_id instead

Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com>
Signed-off-by: Ruslan  Sushko <rsushko@ru.mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:51:55 +01:00
Russell King
c172cc92c8 [ARM] mm 6: allow mem_types table to specify extended pte attributes
Add prot_pte_ext to the mem_types table to allow the extended pte
attributes to be passed to set_pte_ext(), thereby permitting us to
specify memory type information for the hardware PTE entries.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:36:02 +01:00
Russell King
b29e9f5e64 [ARM] mm 5: Use mem_types table in ioremap
We really want to be using the memory type table in ioremap, so we
only have to do the CPU type fixups in one place.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:36:00 +01:00
Russell King
24e6c6996f [ARM] mm 4: make create_mapping() more conventional
Rather than our three separate loops to setup mappings (by page
mappings up to a section boundary, then section mappings, and the
remainder by page mappings) convert this to a more conventional
Linux style of a loop over each page table level.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:35:55 +01:00
Russell King
4a56c1e41f [ARM] mm 3: separate out supersection mappings, avoid for <4GB
Catalin Marinas at ARM Ltd says:
> The CPU architects in ARM intended supersections only as a way to map
> addresses >= 4GB. Supersections are not mandated by the architecture
> and there is no easy way to detect their hardware support at run-time
> (other than checking for a specific core). From the analysis done in
> ARM, there wasn't a clear performance gain by using supersections
> rather than sections (no significant improvement in the TLB misses).

Therefore, we should avoid using supersections unless there's a real
need (iow, we're mapping addresses >= 4GB).

This means that we can simplify create_mapping() a bit since we will
only use supersection mappings for addresses >= 4GB, which means that
the physical, virtual and length must be multiples of the supersection
mapping size.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:35:52 +01:00
Russell King
d5c98176ef [ARM] mm 2: clean up create_mapping()
There's now no need to carry around each protection separately.
Instead, pass around the pointer to the entry in the mem_types
array which we're interested in.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:35:48 +01:00
Russell King
2497f0a812 [ARM] mm 1: Combine mem_type domain into prot_* at init time
Rather than combining the domain for a particular memory type with
the protection information each time we want to use it, do so when
we fix up the mem_type array at initialisation time.

Rename struct mem_types to be mem_type - each structure is one
memory type description, not several.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:35:44 +01:00
Russell King
0f0a00beb8 [ARM] Remove needless linux/ptrace.h includes
Lots of places in arch/arm were needlessly including linux/ptrace.h,
resumably because we used to pass a struct pt_regs to interrupt
handlers.  Now that we don't, all these ptrace.h includes are
redundant.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:34:47 +01:00
Russell King
7ab3f8d595 [ARM] Add ability to dump exception stacks to kernel backtraces
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-04-21 20:34:34 +01:00
Linus Torvalds
874ff01bd9 Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (25 commits)
  Documentation/kernel-docs.txt update.
  arch/cris: typo in KERN_INFO
  Storage class should be before const qualifier
  kernel/printk.c: comment fix
  update I/O sched Kconfig help texts - CFQ is now default, not AS.
  Remove duplicate listing of Cris arch from README
  kbuild: more doc. cleanups
  doc: make doc. for maxcpus= more visible
  drivers/net/eexpress.c: remove duplicate comment
  add a help text for BLK_DEV_GENERIC
  correct a dead URL in the IP_MULTICAST help text
  fix the BAYCOM_SER_HDX help text
  fix SCSI_SCAN_ASYNC help text
  trivial documentation patch for platform.txt
  Fix typos concerning hierarchy
  Fix comment typo "spin_lock_irqrestore".
  Fix misspellings of "agressive".
  drivers/scsi/a100u2w.c: trivial typo patch
  Correct trivial typo in log2.h.
  Remove useless FIND_FIRST_BIT() macro from cardbus.c.
  ...
2007-02-19 13:29:02 -08:00
Russell King
8213084125 Merge NetSilicon NS93xx tree
Fixed conflicts:

	arch/arm/Makefile
	arch/arm/mm/Kconfig

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-18 11:27:07 +00:00
Russell King
f69eda00d4 Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale trees 2007-02-17 20:09:53 +00:00
Uwe Kleine-König
9918cda523 [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 20:05:45 +00:00
Robert P. J. Day
6340aa61b1 kbuild: Replace remaining "depends" with "depends on"
Replace the very few remaining "depends" Kconfig directives with
"depends on".

Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2007-02-17 19:05:24 +01:00
George G. Davis
cb36bb7516 [ARM] 4191/1: Remove redundant __flush_dcache_page() function prototype
Commit 1c9d3df5e8 added function prototype
__flush_dcache_page() in include/asm-arm/cacheflush.h.  So we can remove
the prototype for same in arch/arm/mm/fault-armv.c since it is now
redundant to have it there.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-16 12:57:55 +00:00
Russell King
4ba9dcbeba Merge Realview GIC code 2007-02-15 15:07:40 +00:00
Catalin Marinas
4b17244c13 [ARM] 4109/2: Add support for the RealView/EB MPCore revC platform
The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform. Since the SCU base address was hard-coded in the proc-v6.S
file (and only valid for RealView/EB revB), this patch also adds a
more generic support for defining the SCU information.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-15 14:56:32 +00:00
Imre_Deak
44b1869390 [ARM] 4158/1: Fix user page protection macros
The PAGE_* user page protection macros don't take into account the
configured memory policy and other architecture specific bits like
the global/ASID and shared mapping bits. Instead of constants let
these depend on a variable fixed up at init just like PAGE_KERNEL.

Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-11 17:06:17 +00:00
Catalin Marinas
382266ad5a [ARM] 4135/1: Add support for the L210/L220 cache controllers
This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-11 16:48:02 +00:00
Russell King
f2131d348f [ARM] Always mark ARMv6 PTWs outer cacheable
Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 20:46:20 +00:00
Lennert Buytenhek
3e1a80f11f [ARM] 4153/1: fix consistent_sync() off-by-one BUG check
In consistent_sync(), start + size can end up pointing one byte
beyond the end of the direct RAM mapping.  We shouldn't BUG() when
this happens.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 15:29:00 +00:00
Andrew Victor
b2c6561605 [ARM] 4145/2: AT91: Add support for AT91SAM9263 processor
Add support for the Atmel AT91SAM9263 processor.  It is similar to the
AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc.

Original patch from Nicolas Ferre.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:55:24 +00:00
Russell King
7ae5a761d2 [ARM] Convert DMA cache handling to take const void * args
The DMA cache handling functions take virtual addresses, but in the
form of unsigned long arguments.  This leads to a little confusion
about what exactly they take.  So, convert them to take const void *
instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:44 +00:00
Catalin Marinas
953233dc99 [ARM] 4134/1: Add generic support for outer caches
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:40 +00:00
Catalin Marinas
e6a5d66f58 [ARM] 4129/1: Add barriers after the TLB operations
The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer). The branch target cache invalidation is also needed. The ISB
(Instruction Synchronisation Barrier, formerly Prefetch Flush) is
needed unless there will be a return from exception before the
corresponding mapping is used (i.e. user mappings).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:27 +00:00
Catalin Marinas
9d99df4b10 [ARM] 4128/1: Architecture compliant TTBR changing sequence
On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:24 +00:00
Lennert Buytenhek
850b42933e [ARM] 4123/1: xsc3: general cleanup
This patch cleans up proc-xsc3:
- Correct a number of typos.
- Fix up indentation in a number of places.
- Change references to the various caches to be more clear about
  whether we're talking about the L1 D, the L1 I or the unified L2
  cache.
- Rename "drain write buffer" to "data write barrier", the official
  name used in the Manzano manual.
- Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based
  processor".

Also, since a previously merged patch implements proper support for
using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer
need to enable access to CP0 on boot.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:48:44 +00:00
Catalin Marinas
412489af76 [ARM] 4112/1: Only ioremap to supersections if DOMAIN_IO is zero
Supersections do not have a field for the domain and it is always
0. This patch prevents the creation of supersections during ioremap
when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-25 16:35:26 +00:00
Dan Williams
7f215abc69 [ARM] 4100/1: iop3xx: fix cpu mask for iop333
cosmetic fix so iop333 is not reported as ixp46x
iop333 cpuid = 0x69054210

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-24 11:59:57 +00:00
Russell King
204ecae4e1 [ARM] Fix show_mem() for discontigmem
show_mem() was assuming incorrectly that the mem_map for any
node started at PFN 0.  This is obviously wrong; fix it to
take account of node_start_pfn.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-24 11:59:56 +00:00
Russell King
6020dff092 [ARM] Resolve fuse and direct-IO failures due to missing cache flushes
fuse does not work on ARM due to cache incoherency issues - fuse wants
to use get_user_pages() to copy data from the current process into
kernel space.  However, since this accesses userspace via the kernel
mapping, the kernel mapping can be out of date wrt data written to
userspace.

This can lead to unpredictable behaviour (in the case of fuse) or data
corruption for direct-IO.

This resolves debian bug #402876

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-08 19:49:58 +00:00