Commit Graph

456 Commits

Author SHA1 Message Date
David S. Miller
3763be32d5 [SPARC64]: Define ARCH_HAS_READ_CURRENT_TIMER.
This gives more consistent bogomips and delay() semantics,
especially on sun4v.  It gives weird looking values though...

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:29 -08:00
David S. Miller
3f19a84e39 [SPARC64]: Set associativity of kernel TSB descriptor correctly.
It should be 1, not 0.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:29 -08:00
David S. Miller
c857e3fdbc [SPARC64]: __bzero_noasi --> __clear_user
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:28 -08:00
David S. Miller
46f8604714 [SPARC64]: Put SUN4V ITSB miss into correct trap table entry.
It's 0x9 not 0xb.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:27 -08:00
David S. Miller
3b3ab2eb9c [SPARC64]: Use phys tsb address in tsb_insert() in SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:25 -08:00
David S. Miller
ebd8c56c5a [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.
We need to use the real hardware processor ID when
targetting interrupts, not the "define to 0" thing
the uniprocessor build gives us.

Also, fill in the Node-ID and Agent-ID fields properly
on sun4u/Safari.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:24 -08:00
David S. Miller
101d5c18a9 [SPARC64]: Fix PCI IRQ probing regression.
If the top-level cnode had multi entries in it's "reg"
property, we'd fail.  The buffer wasn't large enough in
such cases.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:23 -08:00
David S. Miller
72aff53f1f [SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile.  We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.

This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.

In order to achieve this:

1) Change sun4v_init_mondo_queues() so that it can operate in
   several modes.

   It can allocate the queues, or install them in the current
   processor, or both.

   The boot cpu does both in it's call early on.

   Later, the boot cpu allocates the sibling cpu queue, starts
   the sibling cpu, then the sibling cpu loads them in.

2) init_cur_cpu_trap() is changed to take the current_thread_info()
   as an argument instead of reading %g6 directly on the current
   cpu.

3) Create a trampoline stack for the sibling cpus.  We do our basic
   kernel calls using this stack, which is locked into the kernel
   image, then go to our proper thread stack after taking over the
   trap table.

4) While we are in this delicate startup state, we put 0xdeadbeef
   into %g4/%g5/%g6 in order to catch accidental accesses.

5) On the final prom_set_trap_table*() call, we put &init_thread_union
   into %g6.  This is a hack to make prom_world(0) work.  All that
   wants to do is restore the %asi register using
   get_thread_current_ds().

Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else.  This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:22 -08:00
David S. Miller
19a0d585e8 [SPARC64]: Disable smp_report_regs() for now.
For 32 cpus and a slow console, it just wedges the
machine especially with DETECT_SOFTLOCKUP enabled.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:21 -08:00
David S. Miller
6154f94f0e [SPARC64]: Rewrite pci_intmap_match().
The whole algorithm was wrong.  What we need to do is:

1) Walk each PCI bus above this device on the path to the
   PCI controller nexus, and for each:
      a) If interrupt-map exists, apply it, record IRQ controller node
      b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus
	 parent OBP node as controller node
      c) Walk up to "controller node" until we hit the first PCI bus
	 in this domain, or "controller node" is the PCI controller
	 OBP node
2) If we walked to PCI controller OBP node, we're done.
3) Else, apply PCI controller interrupt-map to interrupt.

There is some stuff that needs to be checked out for ebus and
isa, but the PCI part is good to go.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:20 -08:00
David S. Miller
14f6689cbb [SPARC64]: Don't set interrupt state to IDLE in enable_irq().
We'll lose events that way.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:20 -08:00
David S. Miller
af02bec662 [SPARC64]: Fix return from trap on SUN4V.
We need to set the global register set _AND_ disable
PSTATE_IE in %pstate.  The original patch sequence was
leaving PSTATE_IE enabled when returning to kernel mode,
oops.

This fixes the random register corruption being seen
on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:19 -08:00
David S. Miller
22780e23c6 [SPARC64]: Set dummy bucket->{imap,iclr} unique on SUN4V.
So that free_irq() disable's the IRQ correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:17 -08:00
David S. Miller
94f8762db9 [SPARC64]: Add sun4v_cpu_qconf() hypervisor call.
Call it from register_one_mondo().

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:16 -08:00
David S. Miller
8e42550c68 [SPARC64]: do_fptrap needs to load the thread reg into %g6.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:14 -08:00
David S. Miller
9b6b46470c [SPARC64]: Fix bogus call to sun4v_mna in winfixup code.
The C function is named sun4v_do_mna not sun4v_mna.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:13 -08:00
David S. Miller
3d6395cb77 [SPARC64]: Fix tl1 trap state capture/dump on SUN4V.
No trap levels above 2 in privileged mode on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:12 -08:00
David S. Miller
e7a0453ef8 [SPARC64] PCI: Size TSB correctly on SUN4V.
Forgot to multiply by 8 * 1024, oops.  Correct the size constant when
the virtual-dma arena is 2GB in size, it should bet 256 not 128.

Finally, log some info about the TSB at probe time.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:10 -08:00
David S. Miller
c7f81d42d3 [SPARC64]: Don't use ASI_QUAD_LDD_PHYS on SUN4V.
Need to use ASI_QUAD_LDD_PHYS_4V instead.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:09 -08:00
David S. Miller
a7b31bac69 [SPARC64]: Do not write garbage into %pstate in tsb_context_switch().
For SUN4V, we were clobbering %o5 to do the hypervisor call.
This clobbers the saved %pstate value and we end up writing
garbage into that register as a result.  Oops.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:08 -08:00
David S. Miller
de635d833f [SPARC64]: Fix flush_tsb_user() on SUN4V.
Needs to use physical addressing just like cheetah_plus.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:07 -08:00
David S. Miller
1daef08a12 [SPARC64]: Fix comment typo in __flush_tlb_kernel_range.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:06 -08:00
David S. Miller
9d29a3fafd [SPARC64]: Decode virtual-devices interrupts correctly.
Need to translate through the interrupt-map{,-mask] properties.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:05 -08:00
David S. Miller
7890f794e0 [SPARC64]: Add prom_{start,stop}cpu_cpuid().
Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu().

We should really test for "SUNW,start-cpu-by-cpuid" presence
and use it if present even on SUN4U.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:04 -08:00
David S. Miller
63c2a0e598 [SPARC64]: Fix pci_intmap_match().
When crawling up the PCI bus chain, stop at the first node
that has an interrupt-map property before we hit the root.

Also, if we use a bus interrupt-{map,mask} do not forget to
update the 'intmask' pointer as we do for the 'intmap' pointer.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:03 -08:00
David S. Miller
ab66a50e31 [SPARC64]: Two IRQ handling fixes.
On SUN4V, force IRQ state to idle in enable_irq().  However,
I'm still not sure this is %100 correct.

Call add_interrupt_randomness() on SUN4V too.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:02 -08:00
David S. Miller
f03b8a5468 [SPARC64]: Use different cache sizing defaults on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:01 -08:00
David S. Miller
329c68b218 [SPARC64]: Make lack of interrupt-map-* a fatal error on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:00 -08:00
David S. Miller
abd92b2d21 [SPARC64]: Fix sun4v_intr_setenabled() return value check in enable_irq().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:59 -08:00
David S. Miller
355db99860 [SPARC64]: Explicitly init *nregs to 0 in find_device_prom_node().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:58 -08:00
David S. Miller
987b6de710 [SPARC64]: Restrict PCI bus scanning on SUN4V.
On the PBM's first bus number, only allow device 0, function 0, to be
poked at with PCI config space accesses.

For some reason, this single device responds to all device numbers.

Also, reduce the verbiage of the debugging log printk's for PCI cfg
space accesses in the SUN4V PCI controller driver, so that it doesn't
overwhelm the slow SUN4V hypervisor console.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:57 -08:00
David S. Miller
9f8a5b843f [SPARC64]: Fix C-function name called by sun4v_mna trap code.
The trap code was calling itself :-)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:56 -08:00
David S. Miller
fbf1c68eaf [SPARC64]: Don't printk() any messaages in sun4v_build_irq().
It just clutters up the log.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:55 -08:00
David S. Miller
e7093703d9 [SPARC64]: INO is never fully specified already on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:54 -08:00
David S. Miller
4a07e646c5 [SPARC64]: Kill sun4v_register_fault_status() on SMP.
That now gets done as a side effect of taking over the
trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:54 -08:00
David S. Miller
3af6e01e9a [SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.h
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:52 -08:00
David S. Miller
c4bea28839 [SPARC64]: Make error codes available from sun4v_intr_get*().
And check for errors at call sites.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:51 -08:00
David S. Miller
4bf447d6f7 [SPARC64]: Pass correct ino to sun4v_intr_*().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:50 -08:00
David S. Miller
a615fea48b [SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:49 -08:00
David S. Miller
7c8f486ae7 [SPARC64]: Fix IOMMU mapping on sun4v.
We should dynamically allocate the per-cpu pglist not use
an in-kernel-image datum, since __pa() does not work on
such addresses.

Also, consistently use "u32" for devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:48 -08:00
David S. Miller
87bdc367ca [SPARC64]: Trim down sun4v IRQ translation kernel log message.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:47 -08:00
David S. Miller
d5a2aa241a [SPARC64] sunhv: Bug fixes.
Add udelay to polling console write loop, and increment
the loop limit.

Name the device "ttyHV" and pass that to add_preferred_console()
when we're using hypervisor console.

Kill sunhv_console_setup(), it's empty.

Handle the case where we don't want to use hypervisor console.
(ie. we have a head attached to a sun4v machine)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:46 -08:00
David S. Miller
e77227eb4e [SPARC64]: Probe virtual-devices root node on sun4v.
This is where we learn how to get the interrupts
for things like the hypervisor console device.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:44 -08:00
David S. Miller
d5eb400430 [SPARC64]: Kill spurious semicolon in sun4v_pci_init().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:43 -08:00
David S. Miller
10951ee610 [SPARC64]: Program IRQ registers correctly on sun4v.
Need to use hypervisor calls instead of direct register
accesses.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:41 -08:00
David S. Miller
e3999574b4 [SPARC64]: Generic sun4v_build_irq().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:40 -08:00
David S. Miller
10804828fd [SPARC64]: More SUN4V PCI work.
Get bus range from child of PCI controller root nexus.
This is actually a hack, but the PCI-E bridge sitting
at the top of the PCI tree responds to PCI config cycles
for every device number, so best to just ignore it for now.

Preliminary PCI irq routing, needs lots of work.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:39 -08:00
David S. Miller
bf941d6cd6 [SPARC64]: Log faulting vaddr when bogus kernel PC detected.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:38 -08:00
David S. Miller
6c0f402f6c [SPARC64]: Implement rest of generic interrupt hypervisor calls.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:37 -08:00
David S. Miller
85dfa19ba9 [SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.S
It is not PCI specific, it is for all system interrupts.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:36 -08:00
David S. Miller
059833eb81 [SPARC64]: Range check bus number in SUN4V PCI controller driver.
It has to be somewhere in the range from pbm->pci_first_busno to
pbm->pci_last_busno, inclusive.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:36 -08:00
David S. Miller
0b522497a1 [SPARC64]: Missing 'return' statement in sun4v_pci_init().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:35 -08:00
David S. Miller
c260926750 [SPARC64]: Implement basic pci_sun4v_scan_bus().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:34 -08:00
David S. Miller
3833789bb2 [SPARC64]: PCI-SUN4V fixes.
Clear top 8-bits of physical addresses in "ranges" property.
This gives the actual physical address.

Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:33 -08:00
David S. Miller
cf627156c4 [SPARC64]: Use inline patching for critical PTE operations.
This handles the SUN4U vs SUN4V PTE layout differences
with near zero performance cost.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:32 -08:00
David S. Miller
ff02e0d26f [SPARC64]: Move PTE field definitions back into asm/pgtable.h
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:31 -08:00
David S. Miller
221b2fb818 [SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.
PCI cfg space is accessed transparently through the Hypervisor and not
through direct cpu PIO operations.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:30 -08:00
David S. Miller
6241e5cc6a [SPARC64]: Fix branch signedness bug in all code patching.
The bug that hit SUN4V TLB patching exists elsewhere.
Make sure we cure all such cases.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:29 -08:00
David S. Miller
1a7a242c89 [SPARC64]: Recognize "virtual-console" as input and output console device.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:28 -08:00
David S. Miller
02fead7505 [SPARC64]: Do not try to synchronize %stick registers on SUN4V.
Writes by privileged code are not allowed.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:27 -08:00
David S. Miller
7aa6264543 [SPARC64]: Do not try to write to %tick or %stick on SUN4V.
Writes by privileged code are disallowed.  The hypervisor manages
the non-privileged bit.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:27 -08:00
David S. Miller
b5a37e96b8 [SPARC64]: Fix mondo queue allocations.
We have to use bootmem during init_IRQ and page alloc
for sibling cpu calls.

Also, fix incorrect hypervisor call return value
checks in the hypervisor SMP cpu mondo send code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:26 -08:00
David S. Miller
c4bce90ea2 [SPARC64]: Deal with PTE layout differences in SUN4V.
Yes, you heard it right, they changed the PTE layout for
SUN4V.  Ho hum...

This is the simple and inefficient way to support this.
It'll get optimized, don't worry.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:25 -08:00
David S. Miller
490384e752 [SPARC64]: Register kernel TSB with hypervisor.
We do this right after we take over the trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:23 -08:00
David S. Miller
459b6e621e [SPARC64]: Fix some SUN4V TLB miss bugs.
Code patching did not sign extend negative branch
offsets correctly.

Kernel TLB miss path needs patching and %g4 register
preservation in order to handle SUN4V correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:23 -08:00
David S. Miller
fd05068d7b [SPARC64]: Fix typo in sun4v_patch().
Second instruction offset is '4' not '3'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:22 -08:00
David S. Miller
6cebb52094 [SPARC64]: Fix sun4v early bootup.
prom_sun4v_name should be "sun4v" not "SUNW,sun4v"

Also, this is too early to make use of the
.sun4v_Xinsn_patch code patching, so just check
things manually.

This gets us at least to prom_init() on Niagara.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:21 -08:00
David S. Miller
0d4bc95b9c [SPARC64]: Fix some Niagara memcpy() bugs.
We need to restore the %asi register properly.
For the kernel this means get_fs(), for user this
means ASI_PNF.

Also, NGcopy_to_user.S was including U3memcpy.S instead
of NGmemcpy.S, oops :-)

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:20 -08:00
David S. Miller
e92b92571c [SPARC64]: Handle hypervisor case correctly in copy_tsb().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:19 -08:00
David S. Miller
4bdff41464 [SPARC64]: Fetch bootup time of day from Hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:17 -08:00
David S. Miller
36a68e77c5 [SPARC64]: Simplify sun4v TLB handling using macros.
There was also a bug in sun4v_itlb_miss, it loaded the
MMU Fault Status base into %g3 instead of %g2.

This pointed out a fast path for TSB miss processing,
since we have %g2 with the MMU Fault Status base, we
can use that to quickly load up the PGD phys address.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:16 -08:00
David S. Miller
12eaa328f9 [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
This is where the virtual address of the fault status
area belongs.

To set it up we don't make a hypervisor call, instead
we call OBP's SUNW,set-trap-table with the real address
of the fault status area as the second argument.  And
right before that call we write the virtual address into
ASI_SCRATCHPAD vaddr 0x0.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:15 -08:00
David S. Miller
1839794464 [SPARC64]: First cut at SUN4V PCI IOMMU handling.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:15 -08:00
David S. Miller
164c220fa3 [SPARC64]: Fix hypervisor call arg passing.
Function goes in %o5, args go in %o0 --> %o5.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:14 -08:00
David S. Miller
7eae642f75 [SPARC64]: Implement SUN4V PCI config space access.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:12 -08:00
David S. Miller
bade562216 [SPARC64]: More SUN4V PCI controller work.
Add assembler file for PCI hypervisor calls.
Setup basic skeleton of SUN4V PCI controller driver.

Add 32-bit devhandle to PBM struct, as this is needed for
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:11 -08:00
David S. Miller
8f6a93a196 [SPARC64]: Beginnings of SUN4V PCI controller support.
Abstract out IOMMU operations so that we can have a different
set of calls on sun4v, which needs to do things through
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:10 -08:00
David S. Miller
4cce4b7cc5 [SPARC64]: Fetch cpu mid properly on sun4v.
If there is a "cpuid" property, use that.  Else suck
it out of the top bits of the "reg" property.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:09 -08:00
David S. Miller
ed6b0b4543 [SPARC64]: SUN4V memory exception trap handlers.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:07 -08:00
David S. Miller
618e9ed98a [SPARC64]: Hypervisor TSB context switching.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:06 -08:00
David S. Miller
aa9143b971 [SPARC64]: Implement sun4v TSB miss handlers.
When we register a TSB with the hypervisor, so that it or hardware can
handle TLB misses and do the TSB walk for us, the hypervisor traps
down to these trap when it incurs a TSB miss.

Processing is simple, we load the missing virtual address and context,
and do a full page table walk.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:05 -08:00
David S. Miller
12816ab38a [SPARC64]: kernel/cpu.c needs asm/spitfire.h
For 'tlb_type'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:05 -08:00
David S. Miller
3a8c069d0e [SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:04 -08:00
David S. Miller
d82ace7dc4 [SPARC64]: Detect sun4v early in boot process.
We look for "SUNW,sun4v" in the 'compatible' property
of the root OBP device tree node.

Protect every %ver register access, to make sure it is
not touched on sun4v, as %ver is hyperprivileged there.

Lock kernel TLB entries using hypervisor calls instead of
calls into OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:03 -08:00
David S. Miller
1d2f1f90a1 [SPARC64]: Sun4v cross-call sending support.
Technically the hypervisor call supports sending in a list
of all cpus to get the cross-call, but I only pass in one
cpu at a time for now.

The multi-cpu support is there, just ifdef'd out so it's easy to
enable or delete it later.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:02 -08:00
David S. Miller
5b0c0572fc [SPARC64]: Sun4v interrupt handling.
Sun4v has 4 interrupt queues: cpu, device, resumable errors,
and non-resumable errors.  A set of head/tail offset pointers
help maintain a work queue in physical memory.  The entries
are 64-bytes in size.

Each queue is allocated then registered with the hypervisor
as we bring cpus up.

The two error queues each get a kernel side buffer that we
use to quickly empty the main interrupt queue before we
call up to C code to log the event and possibly take evasive
action.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:01 -08:00
David S. Miller
ac29c11d4c [SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.
Needs to occur before we enable PSTATE_IE in %pstate.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:12:00 -08:00
David S. Miller
e088ad7ca3 [SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:59 -08:00
David S. Miller
8b11bd12af [SPARC64]: Patch up mmu context register writes for sun4v.
sun4v uses ASI_MMU instead of ASI_DMMU

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:56 -08:00
David S. Miller
481295f982 [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:55 -08:00
David S. Miller
8591e30272 [SPARC64]: Niagara copy/clear page.
Happily we have no D-cache aliasing issues on these
chips, so the implementation is very straightforward.

Add a stub in bootup which will be where the patching
calls will be made for niagara/sun4v/hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:54 -08:00
David S. Miller
df7d6aec96 [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:53 -08:00
David S. Miller
d257d5da39 [SPARC64]: Initial sun4v TLB miss handling infrastructure.
Things are a little tricky because, unlike sun4u, we have
to:

1) do a hypervisor trap to do the TLB load.
2) do the TSB lookup calculations by hand

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:52 -08:00
David S. Miller
840aaef8db [SPARC64]: Add missing memory barriers to instruction patching functions.
V9 requires a write memory barrier before the instruction flush.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:51 -08:00
David S. Miller
45fec05f80 [SPARC64]: Sanitize %pstate writes for sun4v.
If we're just switching between different alternate global
sets, nop it out on sun4v.  Also, get rid of all of the
alternate global save/restore in the OBP CIF trampoline code.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:50 -08:00
David S. Miller
314981ac71 [SPARC64]: Kill all %pstate changes in context switch code.
They are totally unnecessary because:

1) Interrupts are already disabled when switch_to()
   runs.

2) We don't use hard-coded alternate globals any longer.

This found a case in rtrap, which still assumed alternate
global %g6 was current_thread_info(), and that is fixed
by this changeset as well.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:49 -08:00
David S. Miller
936f482af1 [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.
Instead of setting/clearing PSTATE_AG we have to change
the %gl register value on sun4v.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:48 -08:00
David S. Miller
6e02493a7f [SPARC64]: Fill dead cycles on trap entry with real work.
As we save trap state onto the stack, the store buffer fills up
mid-way through and we stall for several cycles as the store buffer
trickles out to the L2 cache.  Meanwhile we can do some privileged
register reads and other calculations, essentially for free.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:47 -08:00
David S. Miller
d96b81533b [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:45 -08:00
David S. Miller
398d108308 [SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:42 -08:00
David S. Miller
a43fe0e789 [SPARC64]: Add some hypervisor tlb_type checks.
And more consistently check cheetah{,_plus} instead
of assuming anything not spitfire is cheetah{,_plus}.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:40 -08:00
David S. Miller
52bf082f0a [SPARC64]: SUN4V hypervisor TLB flush support code.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:38 -08:00
David S. Miller
314ef68597 [SPARC64]: Refine register window trap handling.
When saving and restoing trap state, do the window spill/fill
handling inline so that we never trap deeper than 2 trap levels.
This is important for chips like Niagara.

The window fixup code is massively simplified, and many more
improvements are now possible.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:36 -08:00
David S. Miller
ffe483d552 [SPARC64]: Add explicit register args to trap state loading macros.
This, as well as making the code cleaner, allows a simplification in
the TSB miss handling path.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:35 -08:00
David S. Miller
92704a1c63 [SPARC64]: Refine code sequences to get the cpu id.
On uniprocessor, it's always zero for optimize that.

On SMP, the jmpl to the stub kills the return address stack in the cpu
branch prediction logic, so expand the code sequence inline and use a
code patching section to fix things up.  This also always better and
explicit register selection, which will be taken advantage of in a
future changeset.

The hard_smp_processor_id() function is big, so do not inline it.

Fix up tests for Jalapeno to also test for Serrano chips too.  These
tests want "jbus Ultra-IIIi" cases to match, so that is what we should
test for.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:35 -08:00
David S. Miller
f4e841da30 [SPARC64]: Turn off TSB growing for now.
There are several tricky races involved with growing the TSB.  So just
use base-size TSBs for user contexts and we can revisit enabling this
later.

One part of the SMP problems is that tsb_context_switch() can see
partially updated TSB configuration state if tsb_grow() is running in
parallel.  That's easily solved with a seqlock taken as a writer by
tsb_grow() and taken as a reader to capture all the TSB config state
in tsb_context_switch().

Then there is flush_tsb_user() running in parallel with a tsb_grow().
In theory we could take the seqlock as a reader there too, and just
resample the TSB pointer and reflush but that looks really ugly.

Lastly, I believe there is a case with threads that results in a TSB
entry lock bit being set spuriously which will cause the next access
to that TSB entry to wedge the cpu (since the TSB entry lock bit will
never clear).  It's either copy_tsb() or some bug elsewhere in the TSB
assembly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:34 -08:00
David S. Miller
7bec08e38a [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.
The are distrupting, which by the sparc v9 definition means they
can only occur when interrupts are enabled in the %pstate register.
This never occurs in any of the trap handling code running at
trap levels > 0.

So just mark it as an unexpected trap.

This allows us to kill off the cee_stuff member of struct thread_info.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:33 -08:00
David S. Miller
517af33237 [SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section.  The default uses
virtual addresses, and the patch instructions use physical
address load/stores.

We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:32 -08:00
David S. Miller
30a6ecad96 [SPARC64]: Don't clobber alt-global %g4 on window fixups.
If we are returning back to kernel mode, %g4 could be live
(for example, in the case where we window spill in the etrap
code).  So do not change it's value if going back to kernel.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:30 -08:00
David S. Miller
86b818687d [SPARC64]: Fix race in LOAD_PER_CPU_BASE()
Since we use %g5 itself as a temporary, it can get clobbered
if we take an interrupt mid-stream and thus cause end up with
the final %g5 value too early as a result of rtrap processing.

Set %g5 at the very end, atomically, to avoid this problem.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:29 -08:00
David S. Miller
9954863975 [SPARC64]: Kill swapper_pgd_zero, totally unused.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:28 -08:00
David S. Miller
9bc657b28e [SPARC64]: Fix too early reference to %g6
%g6 is not necessarily set to current_thread_info()
at sparc64_realfault_common.  So store the fault
code and address after we invoke etrap and %g6 is
properly set up.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:27 -08:00
David S. Miller
764afe2edb [SPARC64]: Kill hard-coded %pstate setting in sparc_exit.
Just flip the bit off of whatever it's currently set to.
PSTATE_IE is guarenteed to be enabled when we get here.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:26 -08:00
David S. Miller
2f7ee7c63f [SPARC64]: Increase swapper_tsb size to 32K.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:26 -08:00
David S. Miller
a8b900d801 [SPARC64]: Kill sole argument passed to setup_tba().
No longer used, and move extern declaration to a header file.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:25 -08:00
David S. Miller
3487d1d441 [SPARC64]: Kill PROM locked TLB entry preservation code.
It is totally unnecessary complexity.  After we take over
the trap table, we handle all PROM tlb misses fully.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:24 -08:00
David S. Miller
6b6d017235 [SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()
Instead of ugly hard-coded value.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:23 -08:00
David S. Miller
4da808c352 [SPARC64]: Fix bogus flush instruction usage.
Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization.  That's locked into the TLB
and will always work.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:22 -08:00
David S. Miller
4753eb2ac7 [SPARC64]: Fix incorrect TSB lock bit handling.
The TSB_LOCK_BIT define is actually a special
value shifted down by 32-bits for the assembler
code macros.

In C code, this isn't what we want.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:21 -08:00
David S. Miller
96c6e0d8e2 [SPARC64]: Kill {save,restore}_alternate_globals()
No longer needed now that we no longer have hard-coded
alternate global register usage.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:20 -08:00
David S. Miller
b70c0fa161 [SPARC64]: Preload TSB entries from update_mmu_cache().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:19 -08:00
David S. Miller
bd40791e1d [SPARC64]: Dynamically grow TSB in response to RSS growth.
As the RSS grows, grow the TSB in order to reduce the likelyhood
of hash collisions and thus poor hit rates in the TSB.

This definitely needs some serious tuning.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:18 -08:00
David S. Miller
98c5584cfc [SPARC64]: Add infrastructure for dynamic TSB sizing.
This also cleans up tsb_context_switch().  The assembler
routine is now __tsb_context_switch() and the former is
an inline function that picks out the bits from the mm_struct
and passes it into the assembler code as arguments.

setup_tsb_parms() computes the locked TLB entry to map the
TSB.  Later when we support using the physical address quad
load instructions of Cheetah+ and later, we'll simply use
the physical address for the TSB register value and set
the map virtual and PTE both to zero.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:17 -08:00
David S. Miller
09f94287f7 [SPARC64]: TSB refinements.
Move {init_new,destroy}_context() out of line.

Do not put huge pages into the TSB, only base page size translations.
There are some clever things we could do here, but for now let's be
correct instead of fancy.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:16 -08:00
David S. Miller
56fb4df6da [SPARC64]: Elminate all usage of hard-coded trap globals.
UltraSPARC has special sets of global registers which are switched to
for certain trap types.  There is one set for MMU related traps, one
set of Interrupt Vector processing, and another set (called the
Alternate globals) for all other trap types.

For what seems like forever we've hard coded the values in some of
these trap registers.  Some examples include:

1) Interrupt Vector global %g6 holds current processors interrupt
   work struct where received interrupts are managed for IRQ handler
   dispatch.

2) MMU global %g7 holds the base of the page tables of the currently
   active address space.

3) Alternate global %g6 held the current_thread_info() value.

Such hardcoding has resulted in some serious issues in many areas.
There are some code sequences where having another register available
would help clean up the implementation.  Taking traps such as
cross-calls from the OBP firmware requires some trick code sequences
wherein we have to save away and restore all of the special sets of
global registers when we enter/exit OBP.

We were also using the IMMU TSB register on SMP to hold the per-cpu
area base address, which doesn't work any longer now that we actually
use the TSB facility of the cpu.

The implementation is pretty straight forward.  One tricky bit is
getting the current processor ID as that is different on different cpu
variants.  We use a stub with a fancy calling convention which we
patch at boot time.  The calling convention is that the stub is
branched to and the (PC - 4) to return to is in register %g1.  The cpu
number is left in %g6.  This stub can be invoked by using the
__GET_CPUID macro.

We use an array of per-cpu trap state to store the current thread and
physical address of the current address space's page tables.  The
TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this
table, it uses __GET_CPUID and also clobbers %g1.

TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load
the current processor's IRQ software state into %g6.  It also uses
__GET_CPUID and clobbers %g1.

Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the
current address space's page tables into %g7, it clobbers %g1 and uses
__GET_CPUID.

Many refinements are possible, as well as some tuning, with this stuff
in place.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:16 -08:00
David S. Miller
3c93646524 [SPARC64]: Kill pgtable quicklists and use SLAB.
Taking a nod from the powerpc port.

With the per-cpu caching of both the page allocator and SLAB, the
pgtable quicklist scheme becomes relatively silly and primitive.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:14 -08:00
David S. Miller
05e28f9de6 [SPARC64]: No need to D-cache color page tables any longer.
Unlike the virtual page tables, the new TSB scheme does not
require this ugly hack.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:13 -08:00
David S. Miller
74bf4312ff [SPARC64]: Move away from virtual page tables, part 1.
We now use the TSB hardware assist features of the UltraSPARC
MMUs.

SMP is currently knowingly broken, we need to find another place
to store the per-cpu base pointers.  We hid them away in the TSB
base register, and that obviously will not work any more :-)

Another known broken case is non-8KB base page size.

Also noticed that flush_tlb_all() is not referenced anywhere, only
the internal __flush_tlb_all() (local cpu only) is used by the
sparc64 port, so we can get rid of flush_tlb_all().

The kernel gets it's own 8KB TSB (swapper_tsb) and each address space
gets it's own private 8K TSB.  Later we can add code to dynamically
increase the size of per-process TSB as the RSS grows.  An 8KB TSB is
good enough for up to about a 4MB RSS, after which the TSB starts to
incur many capacity and conflict misses.

We even accumulate OBP translations into the kernel TSB.

Another area for refinement is large page size support.  We could use
a secondary address space TSB to handle those.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:11:13 -08:00
Bernhard R Link
94bbc1763b [SPARC64]: fix sparc_floppy_irq's auxio_register reseting
The patch "[SPARC64]: Get rid of fast IRQ feature"
moved the the code from arch/sparc64/kernel/entry.S:
      lduba           [%g7] ASI_PHYS_BYPASS_EC_E, %g5
      or              %g5, AUXIO_AUX1_FTCNT, %g5
      stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
      andn            %g5, AUXIO_AUX1_FTCNT, %g5
      stba            %g5, [%g7] ASI_PHYS_BYPASS_EC_E
to arch/sparc64/kernel/irq.c:
              val = readb(auxio_register);
              val |= AUXIO_AUX1_FTCNT;
              writeb(val, auxio_register);
              val &= AUXIO_AUX1_FTCNT;
              writeb(val, auxio_register);
This looks like it it missing a bitwise not, which is reintroduced
by this patch.

Due to lack of a floppy device, I could not test it, but it looks
evident.

Signed-off-by: Bernhard R Link <brlink@debian.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:10:34 -08:00
David S. Miller
4d000d5b96 [SPARC64]: Mark __ex_table section correctly.
We must use the "a" (allocate) attribute every time we
emit an entry into the __ex_table section.

For consistency, use "a" instead of #alloc which is some
Solaris compat cruft GNU as provides on Sparc.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-04 23:23:56 -08:00
Linus Torvalds
13f939b5d3 Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 2006-02-26 20:27:11 -08:00
Linus Torvalds
add2b6fdae Make Kprobes depend on modules
Commit 9ec4b1f356 made kprobes not compile
without module support, so just make that clear in the Kconfig file.

Also, since it's marked EXPERIMENTAL, make that dependency explicit too.

Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-26 20:24:40 -08:00
David S. Miller
7abea92145 [SPARC64]: Make cpu_present_map available earlier.
The change to kernel/sched.c's init code to use for_each_cpu()
requires that the cpu_possible_map be setup much earlier.

Set it up via setup_arch(), constrained to NR_CPUS, and later
constrain it to max_cpus in smp_prepare_cpus().

This fixes SMP booting on sparc64.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-26 19:36:00 -08:00
David S. Miller
40ad7a6afc [SPARC]: sys_newfstatat --> sys_fstatat64
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-12 23:30:11 -08:00
Heiko Carstens
642fe301c3 [SPARC64]: Fix sys_newfstatat syscall table entry for 64-bit.
The sparc64 64 bit syscall table seems to be broken as it has
compat_sys_newfstatat in its syscall table instead of sys_newfstatat.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-09 15:09:15 -08:00
David S. Miller
0fc9b55606 [SPARC64]: Update defconfig.
Do not enable CONFIG_LOCALVERSION_AUTO by default.
When doing kernel development it just leaves a ton
of crap around.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-07 18:12:34 -08:00
David S. Miller
1b9a428901 [SPARC]: Wire up sys_unshare().
Also, the Solaris syscall table is sized differrently,
and does not go beyond entry 255, so trim off the excess
entries.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-07 18:11:24 -08:00
David S. Miller
7f7ff6bf02 [SPARC64]: Update defconfig.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-05 00:15:12 -08:00
David S. Miller
3794689dba [SPARC64]: Add .gitignore file for sparc64 boot images.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-05 00:15:11 -08:00
David S. Miller
cddfc12e25 [SPARC64]: Kill compat_sys_clock_settime sign extension stub.
It's wrong and totally unneeded.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-30 01:31:09 -08:00
David S. Miller
4415863773 [SPARC]: Increase NR_SYSCALLS to 299
To let new syscalls through.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-22 12:12:01 -08:00
David S. Miller
3ee68c4af3 [SPARC64]: Use compat_sys_futimesat in 32-bit syscall table.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-20 01:49:15 -08:00
David S. Miller
2d7d5f0511 [SPARC]: Add support for *at(), ppoll, and pselect syscalls.
This also includes by necessity _TIF_RESTORE_SIGMASK support,
which actually resulted in a lot of cleanups.

The sparc signal handling code is quite a mess and I should
clean it up some day.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-19 02:42:49 -08:00
Ulrich Drepper
5590ff0d55 [PATCH] vfs: *at functions: core
Here is a series of patches which introduce in total 13 new system calls
which take a file descriptor/filename pair instead of a single file
name.  These functions, openat etc, have been discussed on numerous
occasions.  They are needed to implement race-free filesystem traversal,
they are necessary to implement a virtual per-thread current working
directory (think multi-threaded backup software), etc.

We have in glibc today implementations of the interfaces which use the
/proc/self/fd magic.  But this code is rather expensive.  Here are some
results (similar to what Jim Meyering posted before).

The test creates a deep directory hierarchy on a tmpfs filesystem.  Then
rm -fr is used to remove all directories.  Without syscall support I get
this:

real    0m31.921s
user    0m0.688s
sys     0m31.234s

With syscall support the results are much better:

real    0m20.699s
user    0m0.536s
sys     0m20.149s

The interfaces are for obvious reasons currently not much used.  But they'll
be used.  coreutils (and Jeff's posixutils) are already using them.
Furthermore, code like ftw/fts in libc (maybe even glob) will also start using
them.  I expect a patch to make follow soon.  Every program which is walking
the filesystem tree will benefit.

Signed-off-by: Ulrich Drepper <drepper@redhat.com>
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Al Viro <viro@ftp.linux.org.uk>
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: Michael Kerrisk <mtk-manpages@gmx.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-18 19:20:29 -08:00
Linus Torvalds
3da38566df Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6 2006-01-18 15:08:02 -08:00
David S. Miller
959a85ada5 [SPARC64]: Fix build with CONFIG_COMPAT disabled.
Based upon a report and preliminary patch from Jim Gifford.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 14:58:05 -08:00
Eddie C. Dost
c126cf80d4 [SPARC64]: Serial Console for E250 Patch
From: Eddie C. Dost <ecd@brainaid.de>

I have the following patch for serial console over the RSC
(remote system controller) on my E250 machine. It basically adds
support for input-device=rsc and output-device=rsc from OBP, and
allows 115200,8,n,1,- serial mode setting.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 14:54:31 -08:00
David S. Miller
c07a8475dd [SPARC64]: Update defconfig.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-18 13:41:36 -08:00
Jesse Brandeburg
35ec56bb78 [PATCH] e1000: Added disable packet split capability
Adds the ability to disability packet split at compile time and use the legacy receive path on PCI express hardware.  Made this a CONFIG option and modified the Kconfig, to reflect the new option.

Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2006-01-18 16:17:57 -05:00
Richard Mortimer
9eb3394bf2 [SPARC64]: Eliminate race condition reading Hummingbird STICK register
Ensure a consistent value is read from the STICK register by ensuring
that both high and low are read without high changing due to a roll
over of the low register.

Various Debian/SPARC users (myself include) have noticed problems with
Hummingbird based systems. The symptoms are that the system time is
seen to jump forward 3 days, 6 hours, 11 minutes give or take a few
seconds. In many cases the system then hangs some time afterwards.

I've spotted a race condition in the code to read the STICK register.
I could not work out why 3d, 6h, 11m is important but guess that it is
due to the 2^32 jump of STICK (forwards on one read and then the next
read will seem to be backwards) during a timer interrupt. I'm guessing
that a change of -2^32 will get converted to a large unsigned
increment after the arithmetic manipulation between STICK,
nanoseconds, jiffies etc.

I did a test where I modified __hbird_read_stick to artificially
inject rollover faults forcefully every few seconds. With this I saw
the clock jump over 6 times in 12 hours compared to once every month
or so.

Signed-off-by: Richard Mortimer <richm@oldelvet.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-01-17 15:21:01 -08:00