Commit Graph

13 Commits

Author SHA1 Message Date
Sam Ravnborg
a1f35ba374 [SPARC64]: Fix of section mismatch warnings.
Fix following Section mismatch warning in sparc64:

WARNING: arch/sparc64/kernel/built-in.o(.text+0x13dec): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'psycho_scan_bus' and 'psycho_pbm_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x14b58): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'sabre_scan_bus' and 'sabre_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x15ea4): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'schizo_scan_bus' and 'schizo_pbm_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x17780): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'pci_sun4v_scan_bus' and 'pci_sun4v_get_head')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x17d5c): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'pci_fire_scan_bus' and 'pci_fire_get_head')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x23860): Section mismatch: reference to .devinit.text:vio_dev_release (between 'vio_create_one' and 'vio_add')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x23868): Section mismatch: reference to .devinit.text:vio_dev_release (between 'vio_create_one' and 'vio_add')

The pci_* were all missing __init annotations.
For the vio.c case it was a function with a wrong annotation which was removed.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-01-21 22:34:30 -08:00
David S. Miller
bbe0b5eb57 [SPARC64]: Kill pci_memspace_mask.
It is totally unnecessary as the needed information is properly
encoded in the resources.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:14 -07:00
David S. Miller
759f89e03c [SPARC64]: Consolidate MSI support code.
This also makes us use the MSI queues correctly.

Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt
handler.  This handler runs the MSI queue and dispatches the
virtual interrupts indicated by arriving MSIs in that MSI queue.

All of the common logic is placed in pci_msi.c, with callbacks to
handle the PCI controller specific aspects of the operations.

This common infrastructure will make it much easier to add MSG
support.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:13 -07:00
David S. Miller
9bb3c227c4 [SPARC64]: Enable MSI on sun4u Fire PCI-E controllers.
The support code is identical to the hypervisor sun4v stuff,
just replacing the hypervisor calls with register reads and
writes in the Fire controller.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-13 21:53:09 -07:00
David S. Miller
ad7ad57c61 [SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling.
Fully unify all of the DMA ops so that subordinate bus types to
the DMA operation providers (such as ebus, isa, of_device) can
work transparently.

Basically, we just make sure that for every system device we
create, the dev->archdata 'iommu' and 'stc' fields are filled
in.

Then we have two platform variants of the DMA ops, one for SUN4U which
actually programs the real hardware, and one for SUN4V which makes
hypervisor calls.

This also fixes the crashes in parport_pc on sparc64, reported by
Meelis Roos.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-30 00:27:34 -07:00
David S. Miller
95d71e663e [SPARC64]: Correct FIRE_IOMMU_FLUSHINV register offset.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-11 21:39:26 -07:00
David S. Miller
ca3dd88e41 [SPARC64] PCI: Consolidate PCI access code into pci_common.c
All the sun4u controllers do the same thing to compute the physical
I/O address to poke, and we can move the sun4v code into this common
location too.

This one needs a bit of testing, in particular the Sabre code had some
funny stuff that would break up u16 and/or u32 accesses into pieces
and I didn't think that was needed any more.  If it is we need to find
out why and add back code to do it again.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-09 02:35:27 -07:00
David S. Miller
c57c2ffb15 [SPARC64]: Kill asm-sparc64/pbm.h
Everything it contains can be hidden in pci_impl.h

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 16:43:08 -07:00
David S. Miller
6c108f1299 [SPARC64]: Move index info pci_pbm_info.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 16:41:40 -07:00
David S. Miller
f1cd8de2c9 [SPARC64]: Move pci_ops into pci_pbm_info.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 16:41:32 -07:00
David S. Miller
34768bc832 [SPARC64] PCI: Use root list of pbm's instead of pci_controller_info's
The idea is to move more and more things into the pbm,
with the eventual goal of eliminating the pci_controller_info
entirely as there really isn't any need for it.

This stage of the transformations requires some reworking of
the PCI error interrupt handling.

It might be tricky to get rid of the pci_controller_info parenting for
a few reasons:

1) When we get an uncorrectable or correctable error we want
   to interrogate the IOMMU and streaming cache of both
   PBMs for error status.  These errors come from the UPA
   front-end which is shared between the two PBM PCI bus
   segments.

   Historically speaking this is why I choose the datastructure
   hierarchy of pci_controller_info-->pci_pbm_info

2) The probing does a portid/devhandle match to look for the
   'other' pbm, but this is entirely an artifact and can be
   eliminated trivially.

What we could do to solve #1 is to have a "buddy" pointer from one pbm
to another.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 16:41:24 -07:00
David S. Miller
cfa0652c4e [SPARC64] PCI: Use common routine to fetch PBM properties.
Namely bus-range and ino-bitmap.

This allows us also to eliminate pci_controller_info's
pci_{first,last}_busno fields as only the pbm ones are
used now.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 16:41:12 -07:00
David S. Miller
861fe90656 [SPARC64]: SUN4U PCI-E controller support.
Some minor refactoring in the generic code was necessary for
this:

1) This controller requires 8-byte access to the interrupt map
   and clear register.  They are 64-bits on all the other
   SBUS and PCI controllers anyways, so this was easy to cure.

2) The IMAP register has a different layout and some bits that we
   need to preserve, so use a read/modify/write when making
   changes to the IMAP register in generic code.

3) Flushing the entire IOMMU TLB is best done with a single write
   to a register on this PCI controller, add a iommu->iommu_flushinv
   for this.

Still lacks MSI support, that will come later.

Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-06 22:44:06 -07:00