Commit Graph

166 Commits

Author SHA1 Message Date
Nicolas Pitre
2d2669b629 [PATCH] ARM: 2651/3: kernel helpers for NPTL support
Patch from Nicolas Pitre

This patch entirely reworks the kernel assistance for NPTL on ARM.
In particular this provides an efficient way to retrieve the TLS
value and perform atomic operations without any instruction emulation
nor special system call.  This even allows for pre ARMv6 binaries to
be forward compatible with SMP systems without any penalty.
The problematic and performance critical operations are performed
through segment of kernel provided user code reachable from user space
at a fixed address in kernel memory.  Those fixed entry points are
within the vector page so we basically get it for free as no extra
memory page is required and nothing else may be mapped at that
location anyway.
This is different from (but doesn't preclude) a full blown VDSO
implementation, however a VDSO would prevent some assembly tricks with
constants that allows for efficient branching to those code segments.
And since those code segments only use a few cycles before returning to
user code, the overhead of a VDSO far call would add a significant
overhead to such minimalistic operations.
The ARM_NR_set_tls syscall also changed number.  This is done for two
reasons:
1) this patch changes the way the TLS value was previously meant to be
   retrieved, therefore we ensure whatever library using the old way
   gets fixed (they only exist in private tree at the moment since the
   NPTL work is still progressing).
2) the previous number was allocated in a range causing an undefined
   instruction trap on kernels not supporting that syscall and it was
   determined that allocating it in a range returning -ENOSYS would be
   much nicer for libraries trying to determine if the feature is
   present or not.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
George G. Davis
3a1e501511 [PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fix
Patch from George G. Davis

As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups.

Signed-off-by: George G. Davis
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
Lennert Buytenhek
458a83fa43 [PATCH] ARM: 2659/1: do not assign PCI I/O address zero on IXP2000
Patch from Lennert Buytenhek

Assigning the address zero to a PCI device BAR causes some part of the
PCI subsystem to believe that resource allocation for that BAR failed
due to resource conflicts, which will make attempts to enable the
device fail.  Work around this by assigning I/O addresses starting
from 00010000.
While we're at it, make the PCI I/O resource end at 0001ffff, since we
only have 64k of outbound I/O window on the IXP2000, and we don't do
bank switching.

Signed-off-by: Lennert Buytenhek
Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 21:58:16 +01:00
Lennert Buytenhek
ae36bf5861 [PATCH] ARM: 2658/1: start ixp2000 pci memory resource at 0xe0000000
Patch from Lennert Buytenhek

On the IXDP2800, the bootloader does an awful job of configuring
the PCI bus, so we make linux reconfigure everything.  Having a 1:1
pci:phys address mapping generally simplifies everything, so try to
allocate PCI addresses from the [e0000000..ffffffff] range, which is
the physical address range of the outbound PCI window on the IXP2000.
This does not affect any of the other IXP2000 platforms since they
all use their bootloader's PCI resource assignment.

Signed-off-by: Lennert Buytenhek
Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 21:58:15 +01:00
Lennert Buytenhek
8443b165f1 [PATCH] ARM: 2657/1: export ixp2000_pci_config_addr
Patch from Lennert Buytenhek

Export ixp2000_pci_config_addr, to be used by the IXDP2800 platform
setup code to coordinate booting the master and slave NPU.

Signed-off-by: Lennert Buytenhek
Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 21:58:15 +01:00
Roland McGrath
c60c390620 [PATCH] x86_64: fix PT_NOTE addition to IA32 vDSO
The addition of the PT_NOTE didn't take in the x86_64 version of the i386
vDSO, because I forgot the linker script bit in that copy.

Signed-off-by: Roland McGrath <roland@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-28 22:47:29 -07:00
Benjamin Herrenschmidt
bdceb6a016 [PATCH] ppc64: Fix return value of some vDSO calls
The ppc vDSO would not properly clear the return value for some calls,
which will be a problem when interfacing those calls with glibc. This
should be fixed before 2.6.12 is released (as it is the first kernel
with the ppc vDSO) so that we don't have to play with symbol versioning
and ugly workarounds.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-27 18:04:45 -07:00
Linus Torvalds
fc67b16eca Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git 2005-04-27 10:05:42 -07:00
Al Viro
efa545791f [PATCH] ppc64: trivial user annotations
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26 11:26:53 -07:00
Linus Torvalds
1e14c33fe2 Automatic merge of kernel.org:/home/rmk/linux-2.6-rmk.git 2005-04-26 08:58:22 -07:00
Al Viro
993fb38b1c [PATCH] amd64 rt_sigframe user annotation
->pretcode in struct rt_sigframe is a userland pointer (and already
treated as such by code using that field). 

Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26 07:43:42 -07:00
Al Viro
66768eb26c [PATCH] ppc-opc NULL noise removal
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-04-26 07:43:41 -07:00
Russell King
bce495d865 [PATCH] ARM: make entry*.S includes more logical
Move common includes to entry-header, and file specific includes
to the relevant file.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:21:02 +01:00
Russell King
f4dc9a4cf2 [PATCH] ARM: Remove single-use user save/restore macros
Assembly macros are pointless if they're only used once.  Move
them inline.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:20:34 +01:00
Russell King
cf88b417f9 [PATCH] ARM: remove PT_TRACESYS
PT_TRACESYS is unused, remove it.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:20:12 +01:00
Russell King
acaca3c915 [PATCH] ARM: Remove SVC_MODE definition
SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h.  Use
the asm/ptrace.h definition instead, and remove SVC_MODE.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:19:48 +01:00
Russell King
e0f9f4a622 [PATCH] ARM: Use __NR_SYSCALL_BASE and __ARM_NR_BASE in asm code
Don't define our own local constants, but use those already defined
in asm/unistd.h instead.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:19:24 +01:00
Russell King
925c8a1a8c [PATCH] ARM: pt_regs offsets
Generate pt_regs S_xx offsets from the structure itself instead
of #defining them.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:18:59 +01:00
Russell King
1ec42c0c97 [PATCH] ARM: Remove argument for disable_irq/enable_irq
Since we do not require a register for these operations, we can
remove this unnecessary argument.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:18:26 +01:00
Russell King
7933523dc7 [PATCH] ARM: remove some entry initialisation asm code
Convert the trivial vector entry initialisation code to C code.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:17:42 +01:00
Linus Torvalds
ab2fd30b66 Automated merge of kernel.org:/home/rmk/linux-2.6-rmk.git 2005-04-25 16:19:32 -07:00
Jeff Lackey
41130d37a4 [PATCH] ARM: 2650/1: PXA27x sleep - workaround Errata 39 & 50 (Patch 2667)
Patch from Jeff Lackey

This patch updates arch/arm/mach-pxa/sleep.S to support
the PXA270 CPU.  It works around Errata 39 & 50 from the
Intel(R) PXA27x Processor Family Specification Update.

Signed-off-by: Jeff Lackey
Signed-off-by: Russell King
2005-04-25 23:38:55 +01:00
Jesse Barnes
605036cf84 From: jbarnes@sgi.com
[IA64] fix ia64 Kconfig to allow CONFIG_PM on sn2

This probably should have been fixed when I fixed up the generic build for
discontig+numa machines, but oh well.

CONFIG_PM is allowable for generic builds but not for sn2 builds, which
doesn't make much sense, and in fact breaks the build if recent ACPI bits are
added to the tree.  It looks like the only arch that needs to prevent
CONFIG_PM stuff is the ski simulator (though those options could probably use
some cleanup as well), so remove the big conditional and replace it with a
simple test for IA64_HP_SIM instead.

Signed-off-by: Jesse Barnes <jbarnes@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:31:04 -07:00
Kenji Kaneshige
b9e41d7fb6 [IA64] iosapic.c: typo ... s/spin_unlock_irq/spin_unlock/
vector sharing patch had a typo ... mismatched spin_lock() with
a spin_unlock_irq().  Fix from Kenji Kaneshige.

Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:27:48 -07:00
Tony Luck
e1ed81ab7a [IA64] print "siblings" before {physical,core,thread} id
Rohit and Suresh changed their mind about the order to print things
in /proc/cpuinfo, but didn't include the change in the version of
the patch they sent to me.

Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:27:12 -07:00
Kenji Kaneshige
24eeb568ae [IA64] vector sharing (Large I/O system support)
Current ia64 linux cannot handle greater than 184 interrupt sources
because of the lack of vectors. The following patch enables ia64 linux
to handle greater than 184 interrupt sources by allowing the same
vector number to be shared by multiple IOSAPIC's RTEs. The design of
this patch is besed on "Intel(R) Itanium(R) Processor Family Interrupt
Architecture Guide".

Even if you don't have a large I/O system, you can see the behavior of
vector sharing by changing IOSAPIC_LAST_DEVICE_VECTOR to fewer value.

Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:26:23 -07:00
Suresh Siddha
e927ecb05e [IA64] multi-core/multi-thread identification
Version 3 - rediffed to apply on top of Ashok's hotplug cpu
patch.  /proc/cpuinfo output in step with x86.

This is an updated MC/MT identification patch based on the 
previous discussions on list. 

Add the Multi-core and Multi-threading detection for IPF.
  - Add new core and threading related fields in /proc/cpuinfo.
		Physical id
		Core id
		Thread id
		Siblings
  - setup the cpu_core_map and cpu_sibling_map appropriately
  - Handles Hot plug CPU
 
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Gordon Jin <gordon.jin@intel.com>
Signed-off-by: Rohit Seth <rohit.seth@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:25:06 -07:00
Keith Owens
6118ec847e [IA64] __copy_user breaks on unaligned src
memcpy_mck.S::__copy_user breaks in the prefetch code under these conditions :-

* src is unaligned and
* dst is near the end of a page and
* the page after dst is unmapped.

Signed-off-by: Keith Owens <kaos@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:23:47 -07:00
Tony Luck
f0a8d3c9ec [IA64] Need to handle lfetch in "no_context" case.
Thanks to Mark for tracking down this one.  Users of __copy_from_user_inatomic()
will be sad if we don't handle lfetch faults for the "no_context" case.

Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:22:44 -07:00
Mark Goodwin
0985ea8f2d [IA64-SGI] Altix SN add support for slots in geoid_t locator
This patch against ia64-test-2.6.12 is needed for forthcoming
Altix chipsets. It renames geoid_any_t to geoid_common_t and
splits the 8bit 'slab' field into two 4bit fields for 'slab'
and 'slot'. Similar changes in the Altix SAL will retain backward
compatibility for old kernels.

Signed-off-by: Mark Goodwin <markgw@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:21:54 -07:00
David Mosberger-Tang
a37d98f6a9 [IA64] fix syscall-optimization goof
Sadly, I goofed in this syscall-tuning patch:

ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com
  [IA64] Improve ia64_leave_syscall() for McKinley-type cores.

  Optimize ia64_leave_syscall() a bit better for McKinley-type cores.
  The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3.
  Good for a 13 cycle improvement.

The problem is that the size of the physical stacked registers was
loaded into the wrong register (r3 instead of r17).  Since r17 by
coincidence always had the value 1, this had the effect of turning
rse_clear_invalid into a no-op.  That poses the risk of leaking kernel
state back to user-land and is hence not acceptable.

The fix below is simple, but unfortunately it costs us about 28 cycles
in syscall overhead. ;-(

Unfortunately, there isn't much we can do about that since those
registers have to be cleared one way or another.

	--david

Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:20:38 -07:00
Russ Anderson
93a07d0a0e [IA64-SGI] Shub2 BTE support - BTE recovery code
patch 2:
	Shub2 BTE recovery code will be implemented in SAL.  
	Define the SAL interface.
	Modify bte_error to call SAL for shub2.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:19:52 -07:00
Russ Anderson
95ff439a51 [IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy.
patch 1:
	Add new MMR definitions.
	Modify BTE initialiation.
	Modify BTE copy.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:19:11 -07:00
Mark Maule
4628d7cada [IA64-SGI] disable TIOCA GART TLB prefetching
Patch to disable SGI TIOCA GART TLB prefetching due to hw bug.

Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:18:02 -07:00
Tony Luck
e96c9b4779 [IA64] MAX_PGT_FREES_PER_PASS must be 'L' to avoid warning
'min' is very picky about types of arguments, make it happy

Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:16:59 -07:00
Alex Williamson
5f6602a101 [IA64] sba_iommu bug fixes
This fixes a couple of bugs in the zx1/sx1000 sba_iommu.  These are
all pretty low likelihood of hitting.  The first problem is a simple off
by one, deep in the sba_alloc_range() error path.  Surrounding that was
a lock ordering problem that could have potentially deadlocked with the
order the locks are grabbed in sba_unmap_single().  I moved the resource
locking into sba_search_bitmap() to prevent this.  Finally, there's a
potential race between unmapping pdir entries and marking incoming DMA
pages clean.  If you see any oddities, please let me know, but I've
tested it pretty thoroughly here.  Tony, please apply.  Thanks,

BTW, many of the options in this driver not on by default are becoming
more and more broken.  I'll be working on some patches to clean them
out, but I wanted to get this bug fix out first.

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:14:36 -07:00
Robin Holt
fde740e4dd [IA64] Percpu quicklist for combined allocator for pgd/pmd/pte.
This patch introduces using the quicklists for pgd, pmd, and pte levels
by combining the alloc and free functions into a common set of routines.
This greatly simplifies the reading of this header file.

This patch is simple but necessary for large numa configurations.
It simply ensures that only pages from the local node are added to a
cpus quicklist.  This prevents the trapping of pages on a remote nodes
quicklist by starting a process, touching a large number of pages to
fill pmd and pte entries, migrating to another node, and then unmapping
or exiting.  With those conditions, the pages get trapped and if the
machine has more than 100 nodes of the same size, the calculation of
the pgtable high water mark will be larger than any single node so page
table cache flushing will never occur.

I ran lmbench lat_proc fork and lat_proc exec on a zx1 with and without
this patch and did not notice any change.

On an sn2 machine, there was a slight improvement which is possibly
due to pages from other nodes trapped on the test node before starting
the run.  I did not investigate further.

This patch shrinks the quicklist based upon free memory on the node
instead of the high/low water marks.  I have written it to enable
preemption periodically and recalculate the amount to shrink every time
we have freed enough pages that the quicklist size should have grown.
I rescan the nodes zones each pass because other processess may be
draining node memory at the same time as we are adding.

Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:13:16 -07:00
Bruce Losure
ff3eb55ed9 [IA64-SGI]
Missed the "bk new" for this file in the last commit.

Signed-off-by: Bruce Losure <blosure@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:12:02 -07:00
Aaron J Young
c1298c5c7e [IA64-SGI] Altix: enable poweroff
This patch adds the necessary "hook" to allow SGI/SN
machines to perform a system power off upon a 
'init 0', 'halt -p', 'poweroff' or 'shutdown -h'.

The "hook" is to set the pm_power_off callback
to ia64_sn_power_down(). pm_power_off is checked
in machine_power_off()/do_poweroff() and, if set, is executed. 
ia64_sn_power_down() is a function already present (but not 
used currently) in the sn kernel.
ia64_sn_power_down() makes a SAL call to execute the
power off.

Signed-off-by: Aaron J Young <ayoung@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:11:14 -07:00
Bruce Losure
e1e19747ec [IA64-SGI] Bus driver for the CX port of SGI's TIO chip.
This patch is to provide CX port infrastructure for SGI TIO-based
h/w.   Also a 'core services' driver for SGI FPGA-based h/w.
                                                                                
Signed-off-by: Bruce Losure <blosure@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:09:41 -07:00
Stephane Eranian
4944930ab7 [IA64] perfmon: make pfm_sysctl a global, and other cleanup
- make pfm_sysctl a global such that it is possible
  to enable/disable debug printk in sampling formats
  using PFM_DEBUG.

- remove unused pfm_debug_var variable

- fix a bug in pfm_handle_work where an BUG_ON() could
  be triggered. There is a path where pfm_handle_work()
  can be called with interrupts enabled, i.e., when
  TIF_NEED_RESCHED is set. The fix correct the masking
  and unmasking of interrupts in pfm_handle_work() such
  that we restore the interrupt mask as it was upon entry.

signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:08:30 -07:00
Colin Ngam
be539c73b5 [IA64-SGI] Shub2 provides an addition of 2 External Interrupt events.
Signed-off-by: Colin Ngam <cngam@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:06:28 -07:00
Mark Goodwin
f1e2a1c8a1 [IA64-SGI] Altix SN topology fix potential infinite loop
Fix infinite loop if sn_hwperf_location_to_bpos() fails.

Signed-off-by: Mark Goodwin <markgw@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:05:08 -07:00
Mark Goodwin
4a5c13c7eb [IA64-SGI] Altix SN topology support for new chipsets and pci topology
please accept this patch to the Altix SN platform topology export
interface to support new chipsets and to export PCI topology.

This follows on top of Jack Steiner's patch dated March 1st
("New chipset support for SN platform").

Signed-off-by: Mark Goodwin <markgw@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:04:22 -07:00
David Mosberger-Tang
30325d1771 [IA64] speed up syscall path a bit more
Recently I noticed that clearing ar.ssd/ar.csd right before srlz.d is
causing significant stalling in the syscall path.  The patch below
fixes that by moving the register-writes after srlz.d.  On a Madison,
this drops break-based getpid() from 241 to 226 cycles (-15 cycles).

Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 13:03:16 -07:00
Keith Owens
e8d1cb2f28 [IA64] Tighten up unw_unwind_to_user check
Detect user space by the unwind frame with predicate PRED_USER_STACK
set, instead of a user space IP.  Tighten up the last ditch check for
running off the top of the kernel stack.

Based on a suggestion by David Mosberger, reworked to fit the current
tree.  This survives my stress test which used to break 2.6.9 kernels.
Unlike 2.6.11, the stress test now unwinds to the correct point, so
gdb can get the user space registers.

Signed-off-by: Keith Owens <kaos@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 11:45:26 -07:00
David Mosberger-Tang
8297511530 [IA64] add missing cpu_relax() in ITC syncing code
Call cpu_relax() in busy-waiting loops of the ITC-syncing code.

Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 11:44:02 -07:00
Mark Maule
9c90bdde77 [IA64-SGI] altix: tioca chip driver (agp)
Provide a driver for the altix TIOCA AGP chipset.  An agpgart backend will
be provided as a separate patch.

Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 11:35:54 -07:00
Mark Maule
9b08ebd167 [IA64-SGI] sn2-move-pci-headers.patch
Move a couple of headers out of arch/ia64/sn/include/pci and into
include/asm-ia64/sn.

Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 11:32:16 -07:00
Mark Maule
e955d82543 [IA64-SGI] sn2-pci-dma-abstraction.patch
Provide an abstraction of the altix pci dma runtime layer so that multiple
pci-based bridges can be supported.

Signed-off-by: Mark Maule <maule@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-04-25 11:26:03 -07:00