To be able to control the cti trigger of each list individually,
instead of using a cti_trig variable to control all link lists.
Change-Id: If81ba94bd02849ec63be16204859f7031bda60bf
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Re-use base address from last entry only when the decs_type of
last entry equal to "DCC_ADDR_TYPE" in dcc_config_add().
Change-Id: I6c678ddaac6c689d73b14c63d03abdbd6289dc0c
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Add dcc region to minidump talbe for new feature. HLOS owned part
of DCC SRAM needs to be added to mini dump.
Change-Id: Ia72720d000e58a811d245c4f330aa6d565ed7203
Signed-off-by: Tao,Zhang <taozha@codeaurora.org>
Disable transaction timeout for now since it causes unexpected
timeout issue. Remove transaction timeout feature for dcc linklist
first.
Change-Id: If22ccbc6b0db228614ee287386ec0ca83dddfdfc
Signed-off-by: Tao,Zhang <taozha@codeaurora.org>
When *ppos + len is overflow, shrink len to max readable size
of SRAM.
Change-Id: I7c35433d384eb596a3f84b7ce13652f58166b40a
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Set transaction timeout to 0x3F for dcc linklist while enabling
dcc hw.
Change-Id: Icb5bc63840d2bb34fc97c87abdc622e81d5c033f
Signed-off-by: Tao,Zhang <taozha@codeaurora.org>
Add support to new register memory map, fix loop offset and
dynamic number of link list.
Change-Id: Ibadfa723842dae80cdd50bf08018d86c2ef30b94
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Signed-off-by: Tao,Zhang <taozha@codeaurora.org>
When it fails to configure any link list, disable all the links and
reset the list config.
Change-Id: Ib315ed47fd9f19cea8b65eeed22ca6e011dd6bab
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Add dcc_sram_memcpy function in dcc driver to compatible with
32bit devices since memcpy_fromio function can't be supported.
Change-Id: I084f0599bbe603e822336e216d656d71ebc841ae
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Add dcc_sram_memset function in dcc_driver since hyp cannot support
virtualize stmgeia instruction in previous inline function
memset_io.
Change-Id: I2f0fc281216d897d33b421fd016a030221cc5c4d
Signed-off-by: Shaoqing Liu <shaoqingliu@codeaurora.org>
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
If set the default value to sram when dcc is enabled, there will be
stuck issue for dcc dump.
Change-Id: I784993d6db41e1afed92ccc05bec0cf1987a3e04
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Reset the lock register if config dcc list fails. Otherwise the list
will be always locked before next dcc_disable.
Change-Id: I2bd209ba84fe4896cce5bf72cdb3d06d2377a383
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Add read_write dt config to support the configure that read an
address's value and then modify the address's value in device tree.
Change-Id: I85c37ed739af8739b87e4dd817dd2e2faf74555f
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Avoid changing curr_list when dcc is enabled. Dcc needs to be disabled
before changing the curr_list. If any link list is enabled,the enable
status of dcc will be true.
Change-Id: I571b172a85b97e3a5e4d55531fad90641283b61e
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
If the config_list is too long,they may beyond the capacity of Dcc sram,
so add verification before dcc_sram_writel.
Change-Id: Id9d4f12830cd52cf84a2cba1a913f0f3b28b4fe5
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
Loop offset of DCC is dynamic according to DCC SRAM size.
Add support to change loop offset according to SRAM size.
Change-Id: I1b0a992fc421ae05f091afe37919edb2ce32a1e1
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
DCC can program multiple link lists. Add driver support to
parse multiple link lists in device tree. Support upto
8 link lists.
Change-Id: Ib8a53253d44f4f8568a7dec079c8713e831c2c4d
Signed-off-by: Shaoqing Liu <shaoqingliu@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
This is a snapshot of the DCC_v2 driver as of msm-4.14
commit 'f7e2b74'("coresight: stm: Fix master control issue").
The second offset present as part of offset descriptor needs
to take into account the length of the first offset. This patch
fixes the current offset calculation to account for it. This
patch removes the clock support since it's not needed.
Fix sscanf issue to prevent buffer overflow.
Change-Id: Iac7463b759efd56b98aa92c594a46a76c3c8d208
Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org>
Signed-off-by: Mulu He <muluhe@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
