mpc52xx/wdt: merge WDT code into the GPT driver
Merge the WDT code into the GPT interface. Signed-off-by: Albrecht Dreß <albrecht.dress@arcor.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Albrecht Dreß
Grant Likely
parent
13b600b59d
commit
eda43d16ef
@ -281,7 +281,8 @@ struct mpc52xx_gpt_priv;
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extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
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extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
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int continuous);
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extern void mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
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extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
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extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
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/* mpc52xx_lpbfifo.c */
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#define MPC52XX_LPBFIFO_FLAG_READ (0)
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@ -16,8 +16,14 @@
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* output signals or measure input signals.
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*
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* This driver supports the GPIO and IRQ controller functions of the GPT
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* device. Timer functions are not yet supported, nor is the watchdog
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* timer.
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* device. Timer functions are not yet supported.
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*
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* The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
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* this prevents the use of any gpt0 gpt function (i.e. they will fail with
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* -EBUSY). Thus, the safety wdt function always has precedence over the gpt
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* function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
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* this means that gpt0 is locked in wdt mode until the next reboot - this
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* may be a requirement in safety applications.
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*
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* To use the GPIO function, the following two properties must be added
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* to the device tree node for the gpt device (typically in the .dts file
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@ -56,11 +62,14 @@
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/miscdevice.h>
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#include <linux/uaccess.h>
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#include <asm/div64.h>
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#include <asm/mpc52xx.h>
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MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
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MODULE_AUTHOR("Sascha Hauer, Grant Likely");
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MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
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MODULE_LICENSE("GPL");
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/**
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@ -70,6 +79,9 @@ MODULE_LICENSE("GPL");
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* @lock: spinlock to coordinate between different functions.
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* @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
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* @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
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* @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
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* if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
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* if the timer is actively used as wdt which blocks gpt functions
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*/
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struct mpc52xx_gpt_priv {
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struct list_head list; /* List of all GPT devices */
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@ -78,6 +90,7 @@ struct mpc52xx_gpt_priv {
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spinlock_t lock;
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struct irq_host *irqhost;
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u32 ipb_freq;
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u8 wdt_mode;
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#if defined(CONFIG_GPIOLIB)
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struct of_gpio_chip of_gc;
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@ -101,14 +114,21 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
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#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
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#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
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#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
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#define MPC52xx_GPT_MODE_WDT_EN (0x8000)
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#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
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#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
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#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
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#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
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#define MPC52xx_GPT_MODE_WDT_PING (0xa5)
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#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
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#define MPC52xx_GPT_CAN_WDT (1 << 0)
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#define MPC52xx_GPT_IS_WDT (1 << 1)
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/* ---------------------------------------------------------------------
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* Cascaded interrupt controller hooks
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*/
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@ -375,16 +395,8 @@ struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
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}
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EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
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/**
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* mpc52xx_gpt_start_timer - Set and enable the GPT timer
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* @gpt: Pointer to gpt private data structure
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* @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
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* @continuous: set to 1 to make timer continuous free running
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*
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* An interrupt will be generated every time the timer fires
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*/
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int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
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int continuous)
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static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
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int continuous, int as_wdt)
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{
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u32 clear, set;
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u64 clocks;
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@ -393,7 +405,10 @@ int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
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clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
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set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
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if (continuous)
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if (as_wdt) {
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clear |= MPC52xx_GPT_MODE_IRQ_EN;
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set |= MPC52xx_GPT_MODE_WDT_EN;
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} else if (continuous)
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set |= MPC52xx_GPT_MODE_CONTINUOUS;
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/* Determine the number of clocks in the requested period. 64 bit
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@ -427,22 +442,279 @@ int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
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return -EINVAL;
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}
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/* Set and enable the timer */
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/* Set and enable the timer, reject an attempt to use a wdt as gpt */
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spin_lock_irqsave(&gpt->lock, flags);
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if (as_wdt)
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gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
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else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
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spin_unlock_irqrestore(&gpt->lock, flags);
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return -EBUSY;
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}
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out_be32(&gpt->regs->count, prescale << 16 | clocks);
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clrsetbits_be32(&gpt->regs->mode, clear, set);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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/**
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* mpc52xx_gpt_start_timer - Set and enable the GPT timer
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* @gpt: Pointer to gpt private data structure
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* @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
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* @continuous: set to 1 to make timer continuous free running
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*
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* An interrupt will be generated every time the timer fires
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*/
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int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
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int continuous)
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{
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return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
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}
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EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
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void mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
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/**
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* mpc52xx_gpt_stop_timer - Stop a gpt
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* @gpt: Pointer to gpt private data structure
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*
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* Returns an error if attempting to stop a wdt
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*/
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int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
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{
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unsigned long flags;
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/* reject the operation if the timer is used as watchdog (gpt 0 only) */
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spin_lock_irqsave(&gpt->lock, flags);
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if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
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spin_unlock_irqrestore(&gpt->lock, flags);
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return -EBUSY;
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}
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clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
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/**
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* mpc52xx_gpt_timer_period - Read the timer period
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* @gpt: Pointer to gpt private data structure
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*
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* Returns the timer period in ns
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*/
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u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
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{
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u64 period;
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u64 prescale;
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unsigned long flags;
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spin_lock_irqsave(&gpt->lock, flags);
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period = in_be32(&gpt->regs->count);
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spin_unlock_irqrestore(&gpt->lock, flags);
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prescale = period >> 16;
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period &= 0xffff;
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if (prescale == 0)
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prescale = 0x10000;
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period = period * prescale * 1000000000ULL;
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do_div(period, (u64)gpt->ipb_freq);
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return period;
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}
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EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
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#if defined(CONFIG_MPC5200_WDT)
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/***********************************************************************
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* Watchdog API for gpt0
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*/
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#define WDT_IDENTITY "mpc52xx watchdog on GPT0"
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/* wdt_is_active stores wether or not the /dev/watchdog device is opened */
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static unsigned long wdt_is_active;
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/* wdt-capable gpt */
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static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
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/* low-level wdt functions */
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static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpt_wdt->lock, flags);
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out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
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spin_unlock_irqrestore(&gpt_wdt->lock, flags);
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}
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/* wdt misc device api */
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static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
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size_t len, loff_t *ppos)
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{
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struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
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mpc52xx_gpt_wdt_ping(gpt_wdt);
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return 0;
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}
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static struct watchdog_info mpc5200_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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.identity = WDT_IDENTITY,
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};
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static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
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int __user *data = (int __user *)arg;
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int timeout;
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u64 real_timeout;
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int ret = 0;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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ret = copy_to_user(data, &mpc5200_wdt_info,
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sizeof(mpc5200_wdt_info));
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if (ret)
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ret = -EFAULT;
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break;
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case WDIOC_GETSTATUS:
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case WDIOC_GETBOOTSTATUS:
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ret = put_user(0, data);
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break;
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case WDIOC_KEEPALIVE:
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mpc52xx_gpt_wdt_ping(gpt_wdt);
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break;
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case WDIOC_SETTIMEOUT:
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ret = get_user(timeout, data);
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if (ret)
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break;
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real_timeout = (u64) timeout * 1000000000ULL;
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ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
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if (ret)
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break;
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/* fall through and return the timeout */
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case WDIOC_GETTIMEOUT:
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/* we need to round here as to avoid e.g. the following
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* situation:
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* - timeout requested is 1 second;
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* - real timeout @33MHz is 999997090ns
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* - the int divide by 10^9 will return 0.
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*/
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real_timeout =
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mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
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do_div(real_timeout, 1000000000ULL);
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timeout = (int) real_timeout;
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ret = put_user(timeout, data);
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break;
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default:
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ret = -ENOTTY;
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}
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return ret;
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}
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static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
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{
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int ret;
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/* sanity check */
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if (!mpc52xx_gpt_wdt)
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return -ENODEV;
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/* /dev/watchdog can only be opened once */
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if (test_and_set_bit(0, &wdt_is_active))
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return -EBUSY;
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/* Set and activate the watchdog with 30 seconds timeout */
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ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
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0, 1);
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if (ret) {
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clear_bit(0, &wdt_is_active);
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return ret;
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}
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file->private_data = mpc52xx_gpt_wdt;
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return nonseekable_open(inode, file);
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}
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static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
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{
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/* note: releasing the wdt in NOWAYOUT-mode does not stop it */
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#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
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struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
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unsigned long flags;
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spin_lock_irqsave(&gpt_wdt->lock, flags);
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clrbits32(&gpt_wdt->regs->mode,
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MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
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gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
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spin_unlock_irqrestore(&gpt_wdt->lock, flags);
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#endif
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clear_bit(0, &wdt_is_active);
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return 0;
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}
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static const struct file_operations mpc52xx_wdt_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = mpc52xx_wdt_write,
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.unlocked_ioctl = mpc52xx_wdt_ioctl,
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.open = mpc52xx_wdt_open,
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.release = mpc52xx_wdt_release,
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};
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static struct miscdevice mpc52xx_wdt_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &mpc52xx_wdt_fops,
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};
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static int __devinit mpc52xx_gpt_wdt_init(void)
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{
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int err;
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/* try to register the watchdog misc device */
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err = misc_register(&mpc52xx_wdt_miscdev);
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if (err)
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pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
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else
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pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
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return err;
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}
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static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
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const u32 *period)
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{
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u64 real_timeout;
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/* remember the gpt for the wdt operation */
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mpc52xx_gpt_wdt = gpt;
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/* configure the wdt if the device tree contained a timeout */
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if (!period || *period == 0)
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return 0;
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real_timeout = (u64) *period * 1000000000ULL;
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if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
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dev_warn(gpt->dev, "starting as wdt failed\n");
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else
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dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
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return 0;
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}
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#else
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static int __devinit mpc52xx_gpt_wdt_init(void)
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{
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return 0;
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}
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#define mpc52xx_gpt_wdt_setup(x, y) (0)
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#endif /* CONFIG_MPC5200_WDT */
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/* ---------------------------------------------------------------------
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* of_platform bus binding code
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*/
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@ -473,6 +745,22 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
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list_add(&gpt->list, &mpc52xx_gpt_list);
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mutex_unlock(&mpc52xx_gpt_list_mutex);
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/* check if this device could be a watchdog */
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if (of_get_property(ofdev->node, "fsl,has-wdt", NULL) ||
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of_get_property(ofdev->node, "has-wdt", NULL)) {
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const u32 *on_boot_wdt;
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gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
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on_boot_wdt = of_get_property(ofdev->node, "fsl,wdt-on-boot",
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NULL);
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if (on_boot_wdt) {
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dev_info(gpt->dev, "used as watchdog\n");
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gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
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} else
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dev_info(gpt->dev, "can function as watchdog\n");
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mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
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}
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return 0;
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}
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@ -507,3 +795,4 @@ static int __init mpc52xx_gpt_init(void)
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/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
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subsys_initcall(mpc52xx_gpt_init);
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device_initcall(mpc52xx_gpt_wdt_init);
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