From cef94393d430e2fcc96cb6d7edec9c57c376521d Mon Sep 17 00:00:00 2001 From: Xiaogang Cui Date: Mon, 16 Dec 2013 16:53:13 +0800 Subject: [PATCH] msm: redefine __raw_{read, write}v for RTB Redefine __raw_readv and __raw_writev for RTB support. Change-Id: Iae7b8e920abc4f23846690d3d1b3d1d933454788 Signed-off-by: Xiaogang Cui lib: iomap: Add MSM RTB support The ioread* and the iowrite* functions and not inlined and hence the RTB logs end up containing the ioread and iowrite functions themselves and not the ones invoking them. Add RTB support to the ioread*and iowrite* functions so that we can get meaningful RTB logs. Note that to avoid multiple RTB logs for ioread* and iowrite* functions, read*_no_log and write*_no_log macros are added. Change-Id: I2315d44c4dfbeee6be4a52f21bf4a20dd9508597 Signed-off-by: Rohit Vaswani Signed-off-by: Rishabh Bhatnagar --- arch/arm64/include/asm/io.h | 98 +++++++++++++++++++++++++++++++------ lib/iomap.c | 23 ++++++--- 2 files changed, 99 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 35b2e50f17fb..d87b9ebac9db 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -30,38 +30,35 @@ #include #include #include +#include #include /* * Generic IO read/write. These perform native-endian accesses. + * that some architectures will want to re-define __raw_{read,write}w. */ -#define __raw_writeb __raw_writeb -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +static inline void __raw_writeb_no_log(u8 val, volatile void __iomem *addr) { asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); } -#define __raw_writew __raw_writew -static inline void __raw_writew(u16 val, volatile void __iomem *addr) +static inline void __raw_writew_no_log(u16 val, volatile void __iomem *addr) { asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); } -#define __raw_writel __raw_writel -static inline void __raw_writel(u32 val, volatile void __iomem *addr) +static inline void __raw_writel_no_log(u32 val, volatile void __iomem *addr) { asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); } -#define __raw_writeq __raw_writeq -static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +static inline void __raw_writeq_no_log(u64 val, volatile void __iomem *addr) { asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); } -#define __raw_readb __raw_readb -static inline u8 __raw_readb(const volatile void __iomem *addr) +static inline u8 __raw_readb_no_log(const volatile void __iomem *addr) { u8 val; asm volatile(ALTERNATIVE("ldrb %w0, [%1]", @@ -71,8 +68,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr) return val; } -#define __raw_readw __raw_readw -static inline u16 __raw_readw(const volatile void __iomem *addr) +static inline u16 __raw_readw_no_log(const volatile void __iomem *addr) { u16 val; @@ -83,8 +79,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) return val; } -#define __raw_readl __raw_readl -static inline u32 __raw_readl(const volatile void __iomem *addr) +static inline u32 __raw_readl_no_log(const volatile void __iomem *addr) { u32 val; asm volatile(ALTERNATIVE("ldr %w0, [%1]", @@ -94,8 +89,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return val; } -#define __raw_readq __raw_readq -static inline u64 __raw_readq(const volatile void __iomem *addr) +static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) { u64 val; asm volatile(ALTERNATIVE("ldr %0, [%1]", @@ -105,6 +99,44 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) return val; } +/* + * There may be cases when clients don't want to support or can't support the + * logging, The appropriate functions can be used but clinets should carefully + * consider why they can't support the logging + */ + +#define __raw_write_logged(v, a, _t) ({ \ + int _ret; \ + void *_addr = (void *)(a); \ + _ret = uncached_logk(LOGK_WRITEL, _addr); \ + ETB_WAYPOINT; \ + __raw_write##_t##_no_log((v), _addr); \ + if (_ret) \ + LOG_BARRIER; \ + }) + +#define __raw_writeb(v, a) __raw_write_logged((v), a, b) +#define __raw_writew(v, a) __raw_write_logged((v), a, w) +#define __raw_writel(v, a) __raw_write_logged((v), a, l) +#define __raw_writeq(v, a) __raw_write_logged((v), a, q) + +#define __raw_read_logged(a, _l, _t) ({ \ + _t __a; \ + void *_addr = (void *)(a); \ + int _ret; \ + _ret = uncached_logk(LOGK_READL, _addr); \ + ETB_WAYPOINT; \ + __a = __raw_read##_l##_no_log(_addr); \ + if (_ret) \ + LOG_BARRIER; \ + __a; \ + }) + +#define __raw_readb(a) __raw_read_logged((a), b, u8) +#define __raw_readw(a) __raw_read_logged((a), w, u16) +#define __raw_readl(a) __raw_read_logged((a), l, u32) +#define __raw_readq(a) __raw_read_logged((a), q, u64) + /* IO barriers */ #define __iormb() rmb() #define __iowmb() wmb() @@ -126,6 +158,22 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) +#define readb_relaxed_no_log(c) ({ u8 __v = __raw_readb_no_log(c); __v; }) +#define readw_relaxed_no_log(c) \ + ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw_no_log(c)); __v; }) +#define readl_relaxed_no_log(c) \ + ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl_no_log(c)); __v; }) +#define readq_relaxed_no_log(c) \ + ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq_no_log(c)); __v; }) + +#define writeb_relaxed_no_log(v, c) ((void)__raw_writeb_no_log((v), (c))) +#define writew_relaxed_no_log(v, c) \ + ((void)__raw_writew_no_log((__force u16)cpu_to_le32(v), (c))) +#define writel_relaxed_no_log(v, c) \ + ((void)__raw_writel_no_log((__force u32)cpu_to_le32(v), (c))) +#define writeq_relaxed_no_log(v, c) \ + ((void)__raw_writeq_no_log((__force u64)cpu_to_le32(v), (c))) + /* * I/O memory access primitives. Reads are ordered relative to any * following Normal memory access. Writes are ordered relative to any prior @@ -141,6 +189,24 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) +#define readb_no_log(c) \ + ({ u8 __v = readb_relaxed_no_log(c); __iormb(); __v; }) +#define readw_no_log(c) \ + ({ u16 __v = readw_relaxed_no_log(c); __iormb(); __v; }) +#define readl_no_log(c) \ + ({ u32 __v = readl_relaxed_no_log(c); __iormb(); __v; }) +#define readq_no_log(c) \ + ({ u64 __v = readq_relaxed_no_log(c); __iormb(); __v; }) + +#define writeb_no_log(v, c) \ + ({ __iowmb(); writeb_relaxed_no_log((v), (c)); }) +#define writew_no_log(v, c) \ + ({ __iowmb(); writew_relaxed_no_log((v), (c)); }) +#define writel_no_log(v, c) \ + ({ __iowmb(); writel_relaxed_no_log((v), (c)); }) +#define writeq_no_log(v, c) \ + ({ __iowmb(); writeq_relaxed_no_log((v), (c)); }) + /* * I/O port access primitives. */ diff --git a/lib/iomap.c b/lib/iomap.c index 541d926da95e..f45ea96c77a2 100644 --- a/lib/iomap.c +++ b/lib/iomap.c @@ -6,6 +6,7 @@ */ #include #include +#include #include @@ -71,26 +72,31 @@ static void bad_io_access(unsigned long port, const char *access) unsigned int ioread8(void __iomem *addr) { - IO_COND(addr, return inb(port), return readb(addr)); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), addr); + IO_COND(addr, return inb(port), return readb_no_log(addr)); return 0xff; } unsigned int ioread16(void __iomem *addr) { - IO_COND(addr, return inw(port), return readw(addr)); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), addr); + IO_COND(addr, return inw(port), return readw_no_log(addr)); return 0xffff; } unsigned int ioread16be(void __iomem *addr) { + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), addr); IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr)); return 0xffff; } unsigned int ioread32(void __iomem *addr) { - IO_COND(addr, return inl(port), return readl(addr)); + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), addr); + IO_COND(addr, return inl(port), return readl_no_log(addr)); return 0xffffffff; } unsigned int ioread32be(void __iomem *addr) { + uncached_logk_pc(LOGK_READL, __builtin_return_address(0), addr); IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr)); return 0xffffffff; } @@ -112,22 +118,27 @@ EXPORT_SYMBOL(ioread32be); void iowrite8(u8 val, void __iomem *addr) { - IO_COND(addr, outb(val,port), writeb(val, addr)); + uncached_logk_pc(LOGK_WRITEL, __builtin_return_address(0), addr); + IO_COND(addr, outb(val, port), writeb_no_log(val, addr)); } void iowrite16(u16 val, void __iomem *addr) { - IO_COND(addr, outw(val,port), writew(val, addr)); + uncached_logk_pc(LOGK_WRITEL, __builtin_return_address(0), addr); + IO_COND(addr, outw(val, port), writew_no_log(val, addr)); } void iowrite16be(u16 val, void __iomem *addr) { + uncached_logk_pc(LOGK_WRITEL, __builtin_return_address(0), addr); IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr)); } void iowrite32(u32 val, void __iomem *addr) { - IO_COND(addr, outl(val,port), writel(val, addr)); + uncached_logk_pc(LOGK_WRITEL, __builtin_return_address(0), addr); + IO_COND(addr, outl(val, port), writel_no_log(val, addr)); } void iowrite32be(u32 val, void __iomem *addr) { + uncached_logk_pc(LOGK_WRITEL, __builtin_return_address(0), addr); IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr)); } EXPORT_SYMBOL(iowrite8);