From b5bac2400f22fddaef4575ca5034db336d67e7f4 Mon Sep 17 00:00:00 2001 From: Abhinav Gupta Date: Thu, 24 Mar 2022 15:47:48 +0530 Subject: [PATCH 1/3] msm: kona_defconfig: Added the flag for ICE Driver as required by FDE Enable the flag required to support ICE Driver for Full Disk Encryption feature. Change-Id: Icd107924f7d1deb1bbb797f155bca8e6aebac72c Signed-off-by: Abhinav Gupta --- arch/arm64/configs/vendor/kona-perf_defconfig | 1 + arch/arm64/configs/vendor/kona_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 5ebdfbb498c5..e239e0608e55 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -719,6 +719,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig index 2b41492b6d6f..ef187b0b0711 100644 --- a/arch/arm64/configs/vendor/kona_defconfig +++ b/arch/arm64/configs/vendor/kona_defconfig @@ -756,6 +756,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y CONFIG_XZ_DEC=y CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y From 66e3c113f822cd6e2b97df6a0178f8577c1f2034 Mon Sep 17 00:00:00 2001 From: Pranav Patel Date: Wed, 6 Jul 2022 17:26:47 +0530 Subject: [PATCH 2/3] msm: kgsl: Use consolidated power level for thermal limit Ensure that thermal limits set by devfreq cooling framework, limits framework and sysfs nodes (like gpu_max_clock) don't overwrite each other, instead a consolidated (lowest of all) limit is used as a final thermal limit. If this fails, fall back to setting thermal_pwrlevel directly. Change-Id: Ia6ec60e4881176da064c3cd5cf4ffd8e0a8e1046 Signed-off-by: Pranav Patel --- drivers/gpu/msm/kgsl_pwrctrl.c | 30 +++++++++++++++++++++++------- drivers/gpu/msm/kgsl_pwrctrl.h | 3 +++ drivers/gpu/msm/kgsl_pwrscale.c | 16 +++++++++++++--- 3 files changed, 39 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index 0832f1993047..efc0e77da52a 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -791,16 +792,19 @@ static ssize_t thermal_pwrlevel_store(struct device *dev, if (ret) return ret; - mutex_lock(&device->mutex); - if (level > pwr->num_pwrlevels - 2) level = pwr->num_pwrlevels - 2; - pwr->thermal_pwrlevel = level; - - /* Update the current level using the new limit */ - kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel); - mutex_unlock(&device->mutex); + if (kgsl_pwr_limits_set_freq(pwr->sysfs_pwr_limit, + pwr->pwrlevels[level].gpu_freq)) { + dev_err(device->dev, + "Failed to set sysfs thermal limit via limits fw\n"); + mutex_lock(&device->mutex); + pwr->thermal_pwrlevel = level; + /* Update the current level using the new limit */ + kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel); + mutex_unlock(&device->mutex); + } return count; } @@ -2426,6 +2430,14 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) if (result) goto error_cleanup_bus_ib; + pwr->cooling_pwr_limit = kgsl_pwr_limits_add(KGSL_DEVICE_3D0); + if (IS_ERR_OR_NULL(pwr->cooling_pwr_limit)) { + dev_err(device->dev, "Failed to add cooling power limit\n"); + result = -EINVAL; + pwr->cooling_pwr_limit = NULL; + goto error_cleanup_bus_ib; + } + INIT_WORK(&pwr->thermal_cycle_ws, kgsl_thermal_cycle); timer_setup(&pwr->thermal_timer, kgsl_thermal_timer, 0); @@ -2475,6 +2487,10 @@ void kgsl_pwrctrl_close(struct kgsl_device *device) kfree(pwr->sysfs_pwr_limit); pwr->sysfs_pwr_limit = NULL; } + + kgsl_pwr_limits_del(pwr->cooling_pwr_limit); + pwr->cooling_pwr_limit = NULL; + kfree(pwr->bus_ib); _close_pcl(pwr); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index 72577d32246c..406486a8f065 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_PWRCTRL_H #define __KGSL_PWRCTRL_H @@ -178,6 +179,7 @@ struct gpu_cx_ipeak_client { * @limits_lock - spin lock to protect limits list * @sysfs_pwr_limit - pointer to the sysfs limits node * @cx_ipeak_pwr_limit - pointer to the cx_ipeak limits node + * @cooling_pwr_limit - pointer to the cooling framework limits node * isense_clk_indx - index of isense clock, 0 if no isense * isense_clk_on_level - isense clock rate is XO rate below this level. * gpu_cx_ipeak_client - CX Ipeak clients used by GPU @@ -237,6 +239,7 @@ struct kgsl_pwrctrl { spinlock_t limits_lock; struct kgsl_pwr_limit *sysfs_pwr_limit; struct kgsl_pwr_limit *cx_ipeak_pwr_limit; + struct kgsl_pwr_limit *cooling_pwr_limit; unsigned int gpu_bimc_int_clk_freq; bool gpu_bimc_interface_enabled; struct gpu_cx_ipeak_client gpu_ipeak_client[2]; diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c index 4fdb5e2edaff..892e9e69f1d0 100644 --- a/drivers/gpu/msm/kgsl_pwrscale.c +++ b/drivers/gpu/msm/kgsl_pwrscale.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include +#include #include "kgsl_device.h" #include "kgsl_pwrscale.h" @@ -900,13 +902,21 @@ static int opp_notify(struct notifier_block *nb, min_level = level; } - pwr->thermal_pwrlevel = max_level; pwr->thermal_pwrlevel_floor = min_level; - /* Update the current level using the new limit */ - kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel); mutex_unlock(&device->mutex); + if (kgsl_pwr_limits_set_freq(pwr->cooling_pwr_limit, + pwr->pwrlevels[max_level].gpu_freq)) { + dev_err(device->dev, + "Failed to set cooling thermal limit via limits fw\n"); + mutex_lock(&device->mutex); + pwr->thermal_pwrlevel = max_level; + /* Update the current level using the new limit */ + kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel); + mutex_unlock(&device->mutex); + } + return 0; } From d6f59978b7c11c32bc628037222e3ee5b5cf4aa0 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Wed, 10 Aug 2022 09:38:46 +0530 Subject: [PATCH 3/3] drivers: thermal: Add valid cpu check in cpu isolate driver Add a check for valid cpu and create cpu isolation cooling device only for those cpu's which passes this check. Change-Id: Ic931a1aa51857ed109555e055879cb39da11f3cf Signed-off-by: Priyansh Jain --- drivers/thermal/qcom/cpu_isolate.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/thermal/qcom/cpu_isolate.c b/drivers/thermal/qcom/cpu_isolate.c index 1d14aa96dcf9..f0340c2b2b51 100644 --- a/drivers/thermal/qcom/cpu_isolate.c +++ b/drivers/thermal/qcom/cpu_isolate.c @@ -318,6 +318,12 @@ static int cpu_isolate_probe(struct platform_device *pdev) break; } } + + if (cpu_isolate_cdev->cpu_id == -1) { + dev_err(&pdev->dev, "Invalid CPU phandle\n"); + continue; + } + INIT_WORK(&cpu_isolate_cdev->reg_work, cpu_isolate_register_cdev); list_add(&cpu_isolate_cdev->node, &cpu_isolate_cdev_list);