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drm/msm/sde: Cache register values when performing clock control

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Remote register I/O amounts to a measurably significant portion of CPU
time due to how frequently this function is used. Cache the value of
each register on-demand and use this value in future invocations to
mitigate the expensive I/O.

Co-authored-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Danny Lin <danny@kdrag0n.dev>
[@0ctobot: Adapted for msm-4.19]
Signed-off-by: Adam W. Willis <return.of.octobot@gmail.com>
This commit is contained in:
Danny Lin 2021-01-19 01:05:38 -05:00 committed by spakkkk
parent aafe02c4d8
commit 98adc65124
3 changed files with 12 additions and 2 deletions
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3
techpack/display/msm/sde/sde_hw_catalog.c
View File

@ -1627,6 +1627,7 @@ static int sde_sspp_parse_dt(struct device_node *np,
sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].bit_off =
PROP_BITVALUE_ACCESS(prop_value,
SSPP_CLK_CTRL, i, 1);
sde_cfg->mdp[j].clk_ctrls[sspp->clk_ctrl].val = -1;
}
SDE_DEBUG(
@ -2140,6 +2141,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].bit_off =
PROP_BITVALUE_ACCESS(prop_value,
WB_CLK_CTRL, i, 1);
sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].val = -1;
}
wb->format_list = sde_cfg->wb_formats;
@ -3636,6 +3638,7 @@ static int sde_parse_reg_dma_dt(struct device_node *np,
sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].bit_off =
PROP_BITVALUE_ACCESS(prop_value,
REG_DMA_CLK_CTRL, 0, 1);
sde_cfg->mdp[i].clk_ctrls[sde_cfg->dma_cfg.clk_ctrl].val = -1;
}
end:

2
techpack/display/msm/sde/sde_hw_catalog.h
View File

@ -739,10 +739,12 @@ enum sde_clk_ctrl_type {
/* struct sde_clk_ctrl_reg : Clock control register
* @reg_off: register offset
* @bit_off: bit offset
* @val: current bit value
*/
struct sde_clk_ctrl_reg {
u32 reg_off;
u32 bit_off;
int val;
};
/* struct sde_mdp_cfg : MDP TOP-BLK instance info

9
techpack/display/msm/sde/sde_hw_top.c
View File

@ -179,6 +179,7 @@ static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp,
static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
enum sde_clk_ctrl_type clk_ctrl, bool enable)
{
struct sde_clk_ctrl_reg *ctrl_reg;
struct sde_hw_blk_reg_map *c;
u32 reg_off, bit_off;
u32 reg_val, new_val;
@ -192,8 +193,12 @@ static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
if (clk_ctrl <= SDE_CLK_CTRL_NONE || clk_ctrl >= SDE_CLK_CTRL_MAX)
return false;
reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
ctrl_reg = (struct sde_clk_ctrl_reg *)&mdp->caps->clk_ctrls[clk_ctrl];
if (cmpxchg(&ctrl_reg->val, !enable, enable) == enable)
return enable;
reg_off = ctrl_reg->reg_off;
bit_off = ctrl_reg->bit_off;
reg_val = SDE_REG_READ(c, reg_off);