Merge commit '64bc95c782fc1e1f6de376f8cf138006a973c9aa' into android12-base

* commit '64bc95c782fc1e1f6de376f8cf138006a973c9aa':
  qcacmn: Dump the rx reo queue descs in ddr
  qcacmn: Add support to configure rate mask to cap phy rate
  qcacmn: Add support to parse a string into uint32 array
  qcacmn: Add cfg_dp_sg_enable to get ini key dp_sg_support

Change-Id: Iccacbc63fb8ab0ea5510d79a32d1c7f8c6d2f688
Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>
This commit is contained in:
UtsavBalar1231 2022-06-08 11:36:57 +05:30
commit 920c8d3641
17 changed files with 440 additions and 12 deletions

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2011-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -288,6 +289,7 @@ enum cdp_host_txrx_stats {
TXRX_SOC_INTERRUPT_STATS = 12,
TXRX_SOC_FSE_STATS = 13,
TXRX_HAL_REG_WRITE_STATS = 14,
TXRX_SOC_REO_HW_DESC_DUMP = 15,
TXRX_HOST_STATS_MAX,
};
@ -2251,6 +2253,7 @@ enum cdp_dp_cfg {
cfg_dp_tso_enable,
cfg_dp_lro_enable,
cfg_dp_gro_enable,
cfg_dp_sg_enable,
cfg_dp_tx_flow_start_queue_offset,
cfg_dp_tx_flow_stop_queue_threshold,
cfg_dp_ipa_uc_tx_buf_size,

View File

@ -314,6 +314,7 @@ struct txrx_pdev_cfg_param_t {
bool gro_enable;
bool tso_enable;
bool lro_enable;
bool sg_enable;
bool enable_data_stall_detection;
bool enable_flow_steering;
bool disable_intra_bss_fwd;

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -347,6 +348,7 @@ const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
{TXRX_FW_STATS_INVALID, TXRX_SOC_INTERRUPT_STATS},
{TXRX_FW_STATS_INVALID, TXRX_SOC_FSE_STATS},
{TXRX_FW_STATS_INVALID, TXRX_HAL_REG_WRITE_STATS},
{TXRX_FW_STATS_INVALID, TXRX_SOC_REO_HW_DESC_DUMP},
};
/* MCL specific functions */
@ -7918,6 +7920,10 @@ dp_print_host_stats(struct dp_vdev *vdev,
hal_dump_reg_write_stats(pdev->soc->hal_soc);
hal_dump_reg_write_srng_stats(pdev->soc->hal_soc);
break;
case TXRX_SOC_REO_HW_DESC_DUMP:
dp_get_rx_reo_queue_info((struct cdp_soc_t *)pdev->soc,
vdev->vdev_id);
break;
default:
dp_info("Wrong Input For TxRx Host Stats");
dp_txrx_stats_help();
@ -10169,6 +10175,9 @@ static uint32_t dp_get_cfg(struct cdp_soc_t *soc, enum cdp_dp_cfg cfg)
case cfg_dp_gro_enable:
value = dpsoc->wlan_cfg_ctx->gro_enabled;
break;
case cfg_dp_sg_enable:
value = dpsoc->wlan_cfg_ctx->sg_enabled;
break;
case cfg_dp_tx_flow_start_queue_offset:
value = dpsoc->wlan_cfg_ctx->tx_flow_start_queue_offset;
break;

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -2014,6 +2015,7 @@ try_desc_alloc:
} else {
hw_qdesc_vaddr = rx_tid->hw_qdesc_vaddr_unaligned;
}
rx_tid->hw_qdesc_vaddr_aligned = hw_qdesc_vaddr;
/* TODO: Ensure that sec_type is set before ADDBA is received.
* Currently this is set based on htt indication
@ -3893,3 +3895,85 @@ void dp_peer_flush_frags(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
dp_peer_unref_delete(peer);
}
#ifdef DUMP_REO_QUEUE_INFO_IN_DDR
void dp_dump_rx_reo_queue_info(
struct dp_soc *soc, void *cb_ctxt, union hal_reo_status *reo_status)
{
struct dp_rx_tid *rx_tid = (struct dp_rx_tid *)cb_ctxt;
if (!rx_tid)
return;
if (reo_status->fl_cache_status.header.status !=
HAL_REO_CMD_SUCCESS) {
dp_err_rl("Rx tid REO HW desc flush failed(%d)",
reo_status->rx_queue_status.header.status);
return;
}
qdf_spin_lock_bh(&rx_tid->tid_lock);
hal_dump_rx_reo_queue_desc(rx_tid->hw_qdesc_vaddr_aligned);
qdf_spin_unlock_bh(&rx_tid->tid_lock);
}
void dp_send_cache_flush_for_rx_tid(
struct dp_soc *soc, struct dp_peer *peer)
{
int i;
struct dp_rx_tid *rx_tid;
struct hal_reo_cmd_params params;
if (!peer) {
dp_err_rl("Peer is NULL");
return;
}
for (i = 0; i < DP_MAX_TIDS; i++) {
rx_tid = &peer->rx_tid[i];
if (!rx_tid)
continue;
qdf_spin_lock_bh(&rx_tid->tid_lock);
if (rx_tid->hw_qdesc_vaddr_aligned) {
qdf_mem_zero(&params, sizeof(params));
params.std.need_status = 1;
params.std.addr_lo =
rx_tid->hw_qdesc_paddr & 0xffffffff;
params.std.addr_hi =
(uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
params.u.fl_cache_params.flush_no_inval = 0;
if (QDF_STATUS_SUCCESS !=
dp_reo_send_cmd(
soc, CMD_FLUSH_CACHE,
&params, dp_dump_rx_reo_queue_info,
(void *)rx_tid)) {
dp_err_rl("cache flush send failed tid %d",
rx_tid->tid);
qdf_spin_unlock_bh(&rx_tid->tid_lock);
break;
}
}
qdf_spin_unlock_bh(&rx_tid->tid_lock);
}
}
void dp_get_rx_reo_queue_info(
struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
{
struct dp_soc *soc = (struct dp_soc *)soc_hdl;
struct dp_vdev *vdev = dp_get_vdev_from_soc_vdev_id_wifi3(soc, vdev_id);
struct dp_peer *peer = NULL;
if (!vdev) {
dp_err_rl("vdev is null for vdev_id: %u", vdev_id);
return;
}
peer = vdev->vap_bss_peer;
if (!peer) {
dp_err_rl("Peer is NULL");
return;
}
dp_send_cache_flush_for_rx_tid(soc, peer);
}
#endif /* DUMP_REO_QUEUE_INFO_IN_DDR */

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -22,6 +23,10 @@
#include <qdf_lock.h>
#include "dp_types.h"
#ifdef DUMP_REO_QUEUE_INFO_IN_DDR
#include "hal_reo.h"
#endif
#define DP_INVALID_PEER_ID 0xffff
#define DP_FW_PEER_STATS_CMP_TIMEOUT_MSEC 5000
@ -338,4 +343,55 @@ dp_peer_update_pkt_capture_params(ol_txrx_soc_handle soc,
void dp_rx_tid_delete_cb(struct dp_soc *soc,
void *cb_ctxt,
union hal_reo_status *reo_status);
#ifdef DUMP_REO_QUEUE_INFO_IN_DDR
/**
* dp_send_cache_flush_for_rx_tid() - Send cache flush cmd to REO per tid
* @soc : dp_soc handle
* @peer: peer
*
* This function is used to send cache flush cmd to reo and
* to register the callback to handle the dumping of the reo
* queue stas from DDR
*
* Return: none
*/
void dp_send_cache_flush_for_rx_tid(
struct dp_soc *soc, struct dp_peer *peer);
/**
* dp_get_rx_reo_queue_info() - Handler to get rx tid info
* @soc : cdp_soc_t handle
* @vdev_id: vdev id
*
* Handler to get rx tid info from DDR after h/w cache is
* invalidated first using the cache flush cmd.
*
* Return: none
*/
void dp_get_rx_reo_queue_info(
struct cdp_soc_t *soc_hdl, uint8_t vdev_id);
/**
* dp_dump_rx_reo_queue_info() - Callback function to dump reo queue stats
* @soc : dp_soc handle
* @cb_ctxt - callback context
* @reo_status: vdev id
*
* This is the callback function registered after sending the reo cmd
* to flush the h/w cache and invalidate it. In the callback the reo
* queue desc info is dumped from DDR.
*
* Return: none
*/
void dp_dump_rx_reo_queue_info(
struct dp_soc *soc, void *cb_ctxt, union hal_reo_status *reo_status);
#else /* DUMP_REO_QUEUE_INFO_IN_DDR */
static inline void dp_get_rx_reo_queue_info(
struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
{
}
#endif /* DUMP_REO_QUEUE_INFO_IN_DDR */
#endif /* _DP_PEER_H_ */

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -729,12 +730,26 @@ void dp_rx_err_handle_bar(struct dp_soc *soc,
start_seq_num);
}
/**
* dp_rx_bar_frame_handle() - Function to handle err BAR frames
* @soc: core DP main context
* @ring_desc: Hal ring desc
* @rx_desc: dp rx desc
* @mpdu_desc_info: mpdu desc info
*
* Handle the error BAR frames received. Ensure the SOC level
* stats are updated based on the REO error code. The BAR frames
* are further processed by updating the Rx tids with the start
* sequence number (SSN) and BA window size. Desc is returned
* to the free desc list
*
* Return: none
*/
static void
dp_rx_bar_frame_handle(struct dp_soc *soc,
hal_ring_desc_t ring_desc,
struct dp_rx_desc *rx_desc,
struct hal_rx_mpdu_desc_info *mpdu_desc_info,
uint8_t error)
struct hal_rx_mpdu_desc_info *mpdu_desc_info)
{
qdf_nbuf_t nbuf;
struct dp_pdev *pdev;
@ -743,6 +758,7 @@ dp_rx_bar_frame_handle(struct dp_soc *soc,
uint16_t peer_id;
uint8_t *rx_tlv_hdr;
uint32_t tid;
uint8_t reo_err_code;
nbuf = rx_desc->nbuf;
rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
@ -763,25 +779,26 @@ dp_rx_bar_frame_handle(struct dp_soc *soc,
if (!peer)
goto next;
reo_err_code = HAL_RX_REO_ERROR_GET(ring_desc);
dp_info("BAR frame: peer = "QDF_MAC_ADDR_FMT
" peer_id = %d"
" tid = %u"
" SSN = %d"
" error status = %d",
" error code = %d",
QDF_MAC_ADDR_REF(peer->mac_addr.raw),
peer_id,
tid,
mpdu_desc_info->mpdu_seq,
error);
reo_err_code);
switch (error) {
switch (reo_err_code) {
case HAL_REO_ERR_BAR_FRAME_2K_JUMP:
DP_STATS_INC(soc,
rx.err.reo_error[error], 1);
rx.err.reo_error[reo_err_code], 1);
case HAL_REO_ERR_BAR_FRAME_OOR:
dp_rx_err_handle_bar(soc, peer, nbuf);
DP_STATS_INC(soc,
rx.err.reo_error[error], 1);
rx.err.reo_error[reo_err_code], 1);
break;
default:
DP_STATS_INC(soc, rx.bar_frame, 1);
@ -1644,8 +1661,7 @@ dp_rx_err_process(struct dp_intr *int_ctx, struct dp_soc *soc,
dp_rx_bar_frame_handle(soc,
ring_desc,
rx_desc,
&mpdu_desc_info,
error);
&mpdu_desc_info);
rx_bufs_reaped[mac_id] += 1;
goto next_entry;

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -586,6 +587,7 @@ struct dp_rx_tid {
uint8_t pn_size;
/* REO TID queue descriptors */
void *hw_qdesc_vaddr_unaligned;
void *hw_qdesc_vaddr_aligned;
qdf_dma_addr_t hw_qdesc_paddr_unaligned;
qdf_dma_addr_t hw_qdesc_paddr;
uint32_t hw_qdesc_alloc_size;

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -27,6 +28,10 @@
#include "hif_io32.h"
#include "qdf_platform.h"
#ifdef DUMP_REO_QUEUE_INFO_IN_DDR
#include "hal_hw_headers.h"
#endif
/* Ring index for WBM2SW2 release ring */
#define HAL_IPA_TX_COMP_RING_IDX 2
@ -2116,6 +2121,78 @@ void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
}
#ifdef DUMP_REO_QUEUE_INFO_IN_DDR
/**
* hal_dump_rx_reo_queue_desc() - Dump reo queue descriptor fields
* @hw_qdesc_vaddr_aligned: Pointer to hw reo queue desc virtual addr
*
* Use the virtual addr pointer to reo h/w queue desc to read
* the values from ddr and log them.
*
* Return: none
*/
static inline void hal_dump_rx_reo_queue_desc(
void *hw_qdesc_vaddr_aligned)
{
struct rx_reo_queue *hw_qdesc =
(struct rx_reo_queue *)hw_qdesc_vaddr_aligned;
if (!hw_qdesc)
return;
hal_info("receive_queue_number %u vld %u window_jump_2k %u"
" hole_count %u ba_window_size %u ignore_ampdu_flag %u"
" svld %u ssn %u current_index %u"
" disable_duplicate_detection %u soft_reorder_enable %u"
" chk_2k_mode %u oor_mode %u mpdu_frames_processed_count %u"
" msdu_frames_processed_count %u total_processed_byte_count %u"
" late_receive_mpdu_count %u seq_2k_error_detected_flag %u"
" pn_error_detected_flag %u current_mpdu_count %u"
" current_msdu_count %u timeout_count %u"
" forward_due_to_bar_count %u duplicate_count %u"
" frames_in_order_count %u bar_received_count %u"
" pn_check_needed %u pn_shall_be_even %u"
" pn_shall_be_uneven %u pn_size %u",
hw_qdesc->receive_queue_number,
hw_qdesc->vld,
hw_qdesc->window_jump_2k,
hw_qdesc->hole_count,
hw_qdesc->ba_window_size,
hw_qdesc->ignore_ampdu_flag,
hw_qdesc->svld,
hw_qdesc->ssn,
hw_qdesc->current_index,
hw_qdesc->disable_duplicate_detection,
hw_qdesc->soft_reorder_enable,
hw_qdesc->chk_2k_mode,
hw_qdesc->oor_mode,
hw_qdesc->mpdu_frames_processed_count,
hw_qdesc->msdu_frames_processed_count,
hw_qdesc->total_processed_byte_count,
hw_qdesc->late_receive_mpdu_count,
hw_qdesc->seq_2k_error_detected_flag,
hw_qdesc->pn_error_detected_flag,
hw_qdesc->current_mpdu_count,
hw_qdesc->current_msdu_count,
hw_qdesc->timeout_count,
hw_qdesc->forward_due_to_bar_count,
hw_qdesc->duplicate_count,
hw_qdesc->frames_in_order_count,
hw_qdesc->bar_received_count,
hw_qdesc->pn_check_needed,
hw_qdesc->pn_shall_be_even,
hw_qdesc->pn_shall_be_uneven,
hw_qdesc->pn_size);
}
#else /* DUMP_REO_QUEUE_INFO_IN_DDR */
static inline void hal_dump_rx_reo_queue_desc(
void *hw_qdesc_vaddr_aligned)
{
}
#endif /* DUMP_REO_QUEUE_INFO_IN_DDR */
/**
* hal_srng_dump_ring_desc() - Dump ring descriptor info
*

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -590,7 +591,7 @@ inline int hal_reo_cmd_flush_cache(hal_ring_handle_t hal_ring_hdl,
BLOCK_CACHE_USAGE_AFTER_FLUSH, cp->block_use_after_flush);
HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, FLUSH_ENTIRE_CACHE,
cp->flush_all);
cp->flush_entire_cache);
if (hif_pm_runtime_get(hal_soc->hif_handle,
RTPM_ID_HAL_REO_CMD) == 0) {

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -179,7 +180,7 @@ struct hal_reo_cmd_flush_queue_params {
* @cache_block_res_index: Blocking resource to be used
* @flush_no_inval: Flush without invalidatig descriptor
* @use_after_flush: Block usage after flush till unblock command
* @flush_all: Flush entire REO cache
* @flush_entire_cache: Flush entire REO cache
*/
struct hal_reo_cmd_flush_cache_params {
bool fwd_mpdus_in_queue;
@ -187,7 +188,7 @@ struct hal_reo_cmd_flush_cache_params {
uint8_t cache_block_res_index;
bool flush_no_inval;
bool block_use_after_flush;
bool flush_all;
bool flush_entire_cache;
};
/**

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -1038,6 +1039,22 @@ struct qdf_ipv6_addr {
*/
QDF_STATUS qdf_ipv6_parse(const char *ipv6_str, struct qdf_ipv6_addr *out_addr);
/**
* qdf_uint32_array_parse() - parse the given string as uint32 array
* @in_str: the input string to parse
* @out_array: the output uint32 array, populated on success
* @array_size: size of the array
* @out_size: size of the populated array
*
* This API is called to convert string (each value separated by
* a comma) into an uint32 array
*
* Return: QDF_STATUS
*/
QDF_STATUS qdf_uint32_array_parse(const char *in_str, uint32_t *out_array,
qdf_size_t array_size, qdf_size_t *out_size);
/**
* qdf_uint16_array_parse() - parse the given string as uint16 array
* @in_str: the input string to parse

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -616,6 +617,55 @@ QDF_STATUS qdf_ipv6_parse(const char *ipv6_str, struct qdf_ipv6_addr *out_addr)
}
qdf_export_symbol(qdf_ipv6_parse);
QDF_STATUS qdf_uint32_array_parse(const char *in_str, uint32_t *out_array,
qdf_size_t array_size, qdf_size_t *out_size)
{
QDF_STATUS status;
bool negate;
qdf_size_t size = 0;
uint64_t value;
QDF_BUG(in_str);
if (!in_str)
return QDF_STATUS_E_INVAL;
QDF_BUG(out_array);
if (!out_array)
return QDF_STATUS_E_INVAL;
QDF_BUG(out_size);
if (!out_size)
return QDF_STATUS_E_INVAL;
while (size < array_size) {
status = __qdf_int_parse_lazy(&in_str, &value, &negate);
if (QDF_IS_STATUS_ERROR(status))
return status;
if ((uint32_t)value != value || negate)
return QDF_STATUS_E_RANGE;
in_str = qdf_str_left_trim(in_str);
switch (in_str[0]) {
case ',':
out_array[size++] = value;
in_str++;
break;
case '\0':
out_array[size++] = value;
*out_size = size;
return QDF_STATUS_SUCCESS;
default:
return QDF_STATUS_E_FAILURE;
}
}
return QDF_STATUS_E_FAILURE;
}
qdf_export_symbol(qdf_uint32_array_parse);
QDF_STATUS qdf_uint16_array_parse(const char *in_str, uint16_t *out_array,
qdf_size_t array_size, qdf_size_t *out_size)
{

View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@ -234,6 +235,80 @@ static uint32_t qdf_types_ut_uint16_array_parse(void)
return errors;
}
#define ut_uint32_array_pass(str, max_size, exp_arr, exp_arr_size) \
__ut_uint32_array(str, QDF_STATUS_SUCCESS, max_size, exp_arr, exp_arr_size)
#define ut_uint32_array_fail(str, max_size, exp_status, exp_arr, exp_arr_size)\
__ut_uint32_array(str, exp_status, max_size, exp_arr, exp_arr_size)
static uint32_t
__ut_uint32_array(const char *str, QDF_STATUS exp_status,
uint8_t max_array_size, uint32_t *exp_array,
uint8_t exp_array_size)
{
uint32_t parsed_array[10];
qdf_size_t parsed_array_size;
QDF_STATUS status;
uint8_t i;
status = qdf_uint32_array_parse(str, parsed_array, max_array_size,
&parsed_array_size);
if (status != exp_status) {
qdf_nofl_alert("FAIL: qdf_uint32_array_parse(\"%s\") -> status %d; expected status %d",
str, status, exp_status);
return 1;
}
if (QDF_IS_STATUS_ERROR(status))
return 0;
if (parsed_array_size != exp_array_size) {
qdf_nofl_alert("FAIL: qdf_uint32_array_parse(\"%s\") -> parsed_array_size %zu; exp_array_size %d",
str, parsed_array_size, exp_array_size);
return 1;
}
for (i = 0; i < exp_array_size; i++)
if (parsed_array[i] != exp_array[i]) {
qdf_nofl_alert("FAIL: qdf_uint32_array_parse(\"%s\") -> parsed_array[%d] %d; exp_array[%d] %d",
str, i, parsed_array[i], i,
exp_array[i]);
return 1;
}
return 0;
}
static uint32_t qdf_types_ut_uint32_array_parse(void)
{
uint32_t errors = 0;
uint32_t exp_array_value[10] = { 1, 100, 9997, 899965, 65536, 0,
4294967295, 268435456,
2164184149, 999999999};
errors += ut_uint32_array_pass(
"1, 100, 9997, 899965, 65536, 0, 4294967295, 268435456, 2164184149, 999999999",
10, exp_array_value, 10);
errors += ut_uint32_array_pass(
"+1, +100, +9997, +899965, +65536, 0, +4294967295, +268435456, +2164184149, +999999999",
10, exp_array_value, 10);
errors += ut_uint32_array_fail("1;", 10, QDF_STATUS_E_FAILURE,
exp_array_value, 0);
/* Out of range test where 4294967296 is out of range */
errors += ut_uint32_array_fail(
"1, 100, 9997, 899965, 65536, 0, 4294967296, 268435456, 2164184149, 999999999",
10, QDF_STATUS_E_RANGE, exp_array_value, 0);
errors += ut_uint32_array_fail(
"-1, -100, -9997, -899965, -65536, 0, -4294967295, -268435456, -2164184149, -999999999",
10, QDF_STATUS_E_RANGE, exp_array_value, 0);
errors += ut_uint32_array_fail(
"1, 100, 9997, 899965, 65536, 日本, 0, 4294967295, 268435456, 999999999",
10, QDF_STATUS_E_FAILURE, exp_array_value, 0);
return errors;
}
#define ut_uint32_pass(str, exp) __ut_uint32(str, QDF_STATUS_SUCCESS, exp)
#define ut_uint32_fail(str, exp_status) __ut_uint32(str, exp_status, 0)
@ -581,6 +656,7 @@ uint32_t qdf_types_unit_test(void)
errors += qdf_types_ut_ipv4_parse();
errors += qdf_types_ut_ipv6_parse();
errors += qdf_types_ut_uint16_array_parse();
errors += qdf_types_ut_uint32_array_parse();
return errors;
}

View File

@ -331,6 +331,7 @@ struct config_fils_params {
* @lower32: Lower 32 bits in the 1st 64-bit value
* @higher32: Higher 32 bits in the 1st 64-bit value
* @lower32_2: Lower 32 bits in the 2nd 64-bit value
* @higher32_2: Higher 32 bits in the 2nd 64-bit value
*/
struct config_ratemask_params {
uint8_t vdev_id;
@ -338,6 +339,7 @@ struct config_ratemask_params {
uint32_t lower32;
uint32_t higher32;
uint32_t lower32_2;
uint32_t higher32_2;
};
/**

View File

@ -578,6 +578,22 @@
CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
"DP LRO Enable")
/*
* <ini>
* CFG_DP_SG - Enable the SG feature standalonely
* @Min: 0
* @Max: 1
* @Default: 1
*
* This ini entry is used to enable/disable SG feature standalonely.
* Also does Rome support SG on TX, lithium does not.
* For example the lithium does not support SG on UDP frames.
* Which is able to handle SG only for TSO frames(in case TSO is enabled).
*
* Usage: External
*
* </ini>
*/
#define CFG_DP_SG \
CFG_INI_BOOL("dp_sg_support", false, \
"DP SG Enable")

View File

@ -3494,6 +3494,22 @@ enum wmi_host_preamble_type {
WMI_HOST_PREAMBLE_HE = 4,
};
/**
* enum wmi_ratemask_type: ratemask type
* @WMI_RATEMASK_TYPE_CCK: CCK rate mask type
* @WMI_RATEMASK_TYPE_HT: HT rate mask type
* @WMI_RATEMASK_TYPE_VHT: VHT rate mask type
* @WMI_RATEMASK_TYPE_HE: HE rate mask type
*
* This is used for 'type' in WMI_VDEV_RATEMASK_CMDID
*/
enum wmi_ratemask_type {
WMI_RATEMASK_TYPE_CCK = 0,
WMI_RATEMASK_TYPE_HT = 1,
WMI_RATEMASK_TYPE_VHT = 2,
WMI_RATEMASK_TYPE_HE = 3,
};
/**
* struct packet_power_info_params - packet power info params
* @chainmask: chain mask

View File

@ -46,6 +46,7 @@ send_vdev_config_ratemask_cmd_tlv(struct wmi_unified *wmi_handle,
cmd->mask_lower32 = param->lower32;
cmd->mask_higher32 = param->higher32;
cmd->mask_lower32_2 = param->lower32_2;
cmd->mask_higher32_2 = param->higher32_2;
wmi_mtrace(WMI_VDEV_RATEMASK_CMDID, cmd->vdev_id, 0);
if (wmi_unified_cmd_send(wmi_handle, buf, len,