R0dn3yS/android_kernel_xiaomi_sm7250
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Merge 227ed6d234 on remote branch

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Change-Id: I1dfbd64c6fbe75b89cbe7d08331ab150f66c8c61
This commit is contained in:
Linux Build Service Account 2022-08-17 07:27:47 -07:00
commit 80b3310a63
6 changed files with 47 additions and 10 deletions
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1
arch/arm64/configs/vendor/kona-perf_defconfig vendored
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@ -719,6 +719,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
CONFIG_CRYPTO_DEV_QCRYPTO=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y

1
arch/arm64/configs/vendor/kona_defconfig vendored
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@ -756,6 +756,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
CONFIG_CRYPTO_DEV_QCRYPTO=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_XZ_DEC=y
CONFIG_PRINTK_TIME=y
CONFIG_DYNAMIC_DEBUG=y

30
drivers/gpu/msm/kgsl_pwrctrl.c
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/msm-bus.h>
@ -791,16 +792,19 @@ static ssize_t thermal_pwrlevel_store(struct device *dev,
if (ret)
return ret;
mutex_lock(&device->mutex);
if (level > pwr->num_pwrlevels - 2)
level = pwr->num_pwrlevels - 2;
pwr->thermal_pwrlevel = level;
/* Update the current level using the new limit */
kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
mutex_unlock(&device->mutex);
if (kgsl_pwr_limits_set_freq(pwr->sysfs_pwr_limit,
pwr->pwrlevels[level].gpu_freq)) {
dev_err(device->dev,
"Failed to set sysfs thermal limit via limits fw\n");
mutex_lock(&device->mutex);
pwr->thermal_pwrlevel = level;
/* Update the current level using the new limit */
kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
mutex_unlock(&device->mutex);
}
return count;
}
@ -2426,6 +2430,14 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
if (result)
goto error_cleanup_bus_ib;
pwr->cooling_pwr_limit = kgsl_pwr_limits_add(KGSL_DEVICE_3D0);
if (IS_ERR_OR_NULL(pwr->cooling_pwr_limit)) {
dev_err(device->dev, "Failed to add cooling power limit\n");
result = -EINVAL;
pwr->cooling_pwr_limit = NULL;
goto error_cleanup_bus_ib;
}
INIT_WORK(&pwr->thermal_cycle_ws, kgsl_thermal_cycle);
timer_setup(&pwr->thermal_timer, kgsl_thermal_timer, 0);
@ -2475,6 +2487,10 @@ void kgsl_pwrctrl_close(struct kgsl_device *device)
kfree(pwr->sysfs_pwr_limit);
pwr->sysfs_pwr_limit = NULL;
}
kgsl_pwr_limits_del(pwr->cooling_pwr_limit);
pwr->cooling_pwr_limit = NULL;
kfree(pwr->bus_ib);
_close_pcl(pwr);

3
drivers/gpu/msm/kgsl_pwrctrl.h
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __KGSL_PWRCTRL_H
#define __KGSL_PWRCTRL_H
@ -178,6 +179,7 @@ struct gpu_cx_ipeak_client {
* @limits_lock - spin lock to protect limits list
* @sysfs_pwr_limit - pointer to the sysfs limits node
* @cx_ipeak_pwr_limit - pointer to the cx_ipeak limits node
* @cooling_pwr_limit - pointer to the cooling framework limits node
* isense_clk_indx - index of isense clock, 0 if no isense
* isense_clk_on_level - isense clock rate is XO rate below this level.
* gpu_cx_ipeak_client - CX Ipeak clients used by GPU
@ -237,6 +239,7 @@ struct kgsl_pwrctrl {
spinlock_t limits_lock;
struct kgsl_pwr_limit *sysfs_pwr_limit;
struct kgsl_pwr_limit *cx_ipeak_pwr_limit;
struct kgsl_pwr_limit *cooling_pwr_limit;
unsigned int gpu_bimc_int_clk_freq;
bool gpu_bimc_interface_enabled;
struct gpu_cx_ipeak_client gpu_ipeak_client[2];

16
drivers/gpu/msm/kgsl_pwrscale.c
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@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/devfreq_cooling.h>
#include <linux/slab.h>
#include <linux/msm_kgsl.h>
#include "kgsl_device.h"
#include "kgsl_pwrscale.h"
@ -900,13 +902,21 @@ static int opp_notify(struct notifier_block *nb,
min_level = level;
}
pwr->thermal_pwrlevel = max_level;
pwr->thermal_pwrlevel_floor = min_level;
/* Update the current level using the new limit */
kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
mutex_unlock(&device->mutex);
if (kgsl_pwr_limits_set_freq(pwr->cooling_pwr_limit,
pwr->pwrlevels[max_level].gpu_freq)) {
dev_err(device->dev,
"Failed to set cooling thermal limit via limits fw\n");
mutex_lock(&device->mutex);
pwr->thermal_pwrlevel = max_level;
/* Update the current level using the new limit */
kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
mutex_unlock(&device->mutex);
}
return 0;
}

6
drivers/thermal/qcom/cpu_isolate.c
View File

@ -318,6 +318,12 @@ static int cpu_isolate_probe(struct platform_device *pdev)
break;
}
}
if (cpu_isolate_cdev->cpu_id == -1) {
dev_err(&pdev->dev, "Invalid CPU phandle\n");
continue;
}
INIT_WORK(&cpu_isolate_cdev->reg_work,
cpu_isolate_register_cdev);
list_add(&cpu_isolate_cdev->node, &cpu_isolate_cdev_list);