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edac: improve gold CPU cache way parsing

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Improve gold CPU cache way parsing. Gold cores uses
bit[31:28] of ERR0MISC0.

Change-Id: I24bd9f1e78829fc37eceb1a09871dab38ec8eacb
Signed-off-by: Prateek Sood <prsood@codeaurora.org>
This commit is contained in:
Prateek Sood 2020-09-21 13:13:27 +05:30
parent ff9ef294fd
commit 6d5f8eda71
1 changed files with 24 additions and 6 deletions
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30
drivers/edac/kryo_arm64_edac.c
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@ -214,6 +214,9 @@ out:
static void dump_err_reg(int errorcode, int level, u64 errxstatus, u64 errxmisc,
struct edac_device_ctl_info *edev_ctl)
{
u32 part_num;
int way;
edac_printk(KERN_CRIT, EDAC_CPU, "ERRXSTATUS_EL1: %llx\n", errxstatus);
edac_printk(KERN_CRIT, EDAC_CPU, "ERRXMISC_EL1: %llx\n", errxmisc);
edac_printk(KERN_CRIT, EDAC_CPU, "Cache level: L%d\n", level + 1);
@ -244,12 +247,27 @@ static void dump_err_reg(int errorcode, int level, u64 errxstatus, u64 errxmisc,
break;
}
if (level == L3)
edac_printk(KERN_CRIT, EDAC_CPU,
"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc));
else
edac_printk(KERN_CRIT, EDAC_CPU,
"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc) >> 2);
if (level == L3) {
way = (int) KRYO_ERRXMISC_WAY(errxmisc);
} else {
part_num = read_cpuid_part_number();
switch (part_num) {
case QCOM_CPU_PART_KRYO4XX_SILVER_V1:
case QCOM_CPU_PART_KRYO4XX_SILVER_V2:
way = (int) KRYO_ERRXMISC_WAY(errxmisc) >> 2;
break;
case QCOM_CPU_PART_KRYO4XX_GOLD:
case QCOM_CPU_PART_KRYO5XX_GOLD:
way = (int) KRYO_ERRXMISC_WAY(errxmisc);
break;
default:
edac_printk(KERN_CRIT, EDAC_CPU,
"Error in matching part num:%u\n", part_num);
return;
}
}
edac_printk(KERN_CRIT, EDAC_CPU, "Way: %d\n", way);
errors[errorcode].func(edev_ctl, smp_processor_id(),
level, errors[errorcode].msg);
}