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Merge branch 'drm-radeon-testing' of /ssd/git/drm-radeon-next into drm-next-stage

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* 'drm-radeon-testing' of /ssd/git/drm-radeon-next:
  drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond
  drm/ttm: fix function prototype to match implementation
  drm/radeon: use ALIGN instead of open coding it
  drm/radeon/kms: initialize set_surface_reg reg for rs600 asic
This commit is contained in:
Dave Airlie 2010-03-01 16:08:57 +10:00
commit 68de774582
7 changed files with 15 additions and 4 deletions
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2
drivers/gpu/drm/radeon/r600_blit.c
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@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64
RING_LOCALS;
DRM_DEBUG("\n");
h = (h + 7) & ~7;
h = ALIGN(h, 8);
if (h < 8)
h = 8;

4
drivers/gpu/drm/radeon/r600_blit_kms.c
View File

@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format,
u32 cb_color_info;
int pitch, slice;
h = (h + 7) & ~7;
h = ALIGN(h, 8);
if (h < 8)
h = 8;
@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev)
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
/* emit an IB pointing at default state */
dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);

2
drivers/gpu/drm/radeon/radeon_asic.h
View File

@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = {
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg,
.bandwidth_update = &rs600_bandwidth_update,
.hpd_init = &rs600_hpd_init,
.hpd_fini = &rs600_hpd_fini,

1
drivers/gpu/drm/radeon/radeon_cp.c
View File

@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
dev_priv->have_z_offset = 0;
radeon_do_engine_reset(dev);
radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);

2
drivers/gpu/drm/radeon/radeon_drv.h
View File

@ -268,6 +268,8 @@ typedef struct drm_radeon_private {
u32 scratch_ages[5];
int have_z_offset;
/* starting from here on, data is preserved accross an open */
uint32_t flags; /* see radeon_chip_flags */
resource_size_t fb_aper_offset;

6
drivers/gpu/drm/radeon/radeon_state.c
View File

@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
DRM_ERROR("Invalid depth buffer offset\n");
return -EINVAL;
}
dev_priv->have_z_offset = 1;
break;
case RADEON_EMIT_PP_CNTL:
@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
if (tmp & RADEON_BACK)
flags |= RADEON_FRONT;
}
if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
if (!dev_priv->have_z_offset)
printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
}
if (flags & (RADEON_FRONT | RADEON_BACK)) {

2
include/drm/ttm/ttm_bo_driver.h
View File

@ -908,7 +908,7 @@ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
* Utility function that returns the pgprot_t that should be used for
* setting up a PTE with the caching model indicated by @c_state.
*/
extern pgprot_t ttm_io_prot(enum ttm_caching_state c_state, pgprot_t tmp);
extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
#define TTM_HAS_AGP