From 2955ad3457e73bcf6ee9585ba3291b38b96940c6 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 6 Aug 2019 16:01:16 -0700 Subject: [PATCH] msm: pcie: make PCIe DRV L1ss timeout configurable in devicetree Every client have different requirements for when to enter L1ss sleep. Add support to configure the DRV L1ss timeout in devicetree. Change-Id: I3f2b3f65a0ff9511ec738c6fd681a03c32048955 Signed-off-by: Tony Truong --- drivers/pci/controller/pci-msm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 4db3c0e153a0..3aaec11fcf92 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -5931,12 +5931,22 @@ static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev, struct msm_pcie_drv_msg *msg; struct msm_pcie_drv_tre *pkt; struct msm_pcie_drv_header *hdr; + u32 drv_l1ss_timeout_us = 0; + int ret; drv_info = devm_kzalloc(&pcie_dev->pdev->dev, sizeof(*drv_info), GFP_KERNEL); if (!drv_info) return -ENOMEM; + ret = of_property_read_u32(of_node, "qcom,drv-l1ss-timeout-us", + &drv_l1ss_timeout_us); + if (ret) + drv_l1ss_timeout_us = L1SS_TIMEOUT_US; + + PCIE_DBG(pcie_dev, "PCIe: RC%d: DRV L1ss timeout: %dus\n", + pcie_dev->rc_idx, drv_l1ss_timeout_us); + drv_info->dev_id = pcie_dev->rc_idx; /* cache frequent command for communication */ @@ -5951,7 +5961,7 @@ static int msm_pcie_setup_drv(struct msm_pcie_dev_t *pcie_dev, pkt->dword[0] = MSM_PCIE_DRV_CMD_ENABLE; pkt->dword[1] = hdr->dev_id; - pkt->dword[2] = L1SS_TIMEOUT_US / 1000; + pkt->dword[2] = drv_l1ss_timeout_us / 1000; msg = &drv_info->drv_disable; pkt = &msg->pkt;