usb: phy: Add snapshot of PHY msm usb driver
This change adds PHY msm usb driver which handles PHY initialization,
clock management,and workarounds required after resetting the
hardware and power management.
This snapshot is taken as of msm-4.14 'commit 86918472c0fd
("ARM: dts: msm: support A/B OTA for LW.2.0")'.
This change also fixes the compilation errors.
Change-Id: I5f262a097a87393b5eeffa3f3ae3e21088ef53f1
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
This commit is contained in:
Ajay Agarwal
Gerrit - the friendly Code Review server
parent
502f654139
commit
0cdacf611f
@ -137,6 +137,20 @@ config USB_ISP1301
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To compile this driver as a module, choose M here: the
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module will be called phy-isp1301.
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config USB_MSM_OTG
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tristate "Qualcomm Technologies, Inc. USB OTG controller support"
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depends on (USB || USB_GADGET) && (ARCH_QCOM || COMPILE_TEST)
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depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
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depends on RESET_CONTROLLER
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select USB_PHY
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help
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Enable this to support the USB OTG transceiver on the chipset.
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It handles PHY initialization, clock management, and workarounds required
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after resetting the hardware and power management.
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This driver is required even for peripheral only or host only
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mode configurations. This driver is not supported on boards like trout which
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has an external PHY.
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config USB_MSM_SSPHY_QMP
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tristate "MSM SSUSB QMP PHY Driver"
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depends on ARCH_QCOM
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@ -28,3 +28,4 @@ obj-$(CONFIG_KEYSTONE_USB_PHY) += phy-keystone.o
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obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o phy-msm-qusb-v2.o
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obj-$(CONFIG_USB_MSM_SSPHY_QMP) += phy-msm-ssusb-qmp.o
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obj-$(CONFIG_MSM_HSUSB_PHY) += phy-msm-snps-hs.o
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obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
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5049
drivers/usb/phy/phy-msm-usb.c
Normal file
5049
drivers/usb/phy/phy-msm-usb.c
Normal file
File diff suppressed because it is too large
Load Diff
346
include/linux/usb/msm_hsusb.h
Normal file
346
include/linux/usb/msm_hsusb.h
Normal file
@ -0,0 +1,346 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* include/linux/usb/msm_hsusb.h
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*
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* Copyright (C) 2008 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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* Copyright (c) 2009-2021 The Linux Foundation. All rights reserved.
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*
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*/
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#ifndef __ASM_ARCH_MSM_HSUSB_H
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#define __ASM_ARCH_MSM_HSUSB_H
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#include <linux/types.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/otg.h>
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#include <linux/clk.h>
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#include <linux/pm_qos.h>
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#include <linux/hrtimer.h>
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#include <linux/power_supply.h>
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#include <linux/cdev.h>
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#include <linux/usb_bam.h>
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#include <linux/extcon.h>
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#include <linux/regulator/driver.h>
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/**
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* Used different VDDCX voltage values
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*/
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enum usb_vdd_value {
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VDD_NONE = 0,
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VDD_MIN,
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VDD_MAX,
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VDD_VAL_MAX,
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};
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/**
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* Requested USB votes for NOC frequency
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*
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* USB_NOC_NOM_VOTE Vote for NOM set of NOC frequencies
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* USB_NOC_SVS_VOTE Vote for SVS set of NOC frequencies
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*
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*/
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enum usb_noc_mode {
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USB_NOC_NOM_VOTE = 0,
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USB_NOC_SVS_VOTE,
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USB_NOC_NUM_VOTE,
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};
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/**
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* Different states involved in USB charger detection.
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*
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* USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
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* process is not yet started.
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* USB_CHG_STATE_IN_PROGRESS Charger detection in progress
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* USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
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* USB_CHG_STATE_DCD_DONE Data pin contact is detected.
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* USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
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* between SDP and DCP/CDP).
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* USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
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* between DCP and CDP).
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* USB_CHG_STATE_DETECTED USB charger type is determined.
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* USB_CHG_STATE_QUEUE_SM_WORK SM work to start/stop gadget is queued.
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*
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*/
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enum usb_chg_state {
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USB_CHG_STATE_UNDEFINED = 0,
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USB_CHG_STATE_IN_PROGRESS,
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USB_CHG_STATE_WAIT_FOR_DCD,
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USB_CHG_STATE_DCD_DONE,
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USB_CHG_STATE_PRIMARY_DONE,
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USB_CHG_STATE_SECONDARY_DONE,
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USB_CHG_STATE_DETECTED,
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USB_CHG_STATE_QUEUE_SM_WORK,
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};
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/**
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* USB charger types
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*
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* USB_INVALID_CHARGER Invalid USB charger.
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* USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
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* on USB2.0 compliant host/hub.
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* USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
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* USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
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* IDEV_CHG_MAX can be drawn irrespective of USB state.
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* USB_NONCOMPLIANT_CHARGER A non-compliant charger pull DP and DM to specific
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* voltages between 2.0-3.3v for identification.
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*
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*/
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enum usb_chg_type {
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USB_INVALID_CHARGER = 0,
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USB_SDP_CHARGER,
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USB_DCP_CHARGER,
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USB_CDP_CHARGER,
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USB_NONCOMPLIANT_CHARGER,
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USB_FLOATED_CHARGER,
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};
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/**
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* Maintain state for hvdcp external charger status
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* DEFAULT This is used when DCP is detected
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* ACTIVE This is used when ioctl is called to block LPM
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* INACTIVE This is used when ioctl is called to unblock LPM
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*/
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enum usb_ext_chg_status {
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DEFAULT = 1,
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ACTIVE,
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INACTIVE,
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};
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/**
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* USB ID state
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*/
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enum usb_id_state {
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USB_ID_GROUND = 0,
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USB_ID_FLOAT,
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};
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#define USB_NUM_BUS_CLOCKS 3
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/**
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* struct msm_otg: OTG driver data. Shared by HCD and DCD.
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* @otg: USB OTG Transceiver structure.
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* @pdata: otg device platform data.
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* @irq: IRQ number assigned for HSUSB controller.
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* @async_irq: IRQ number used by some controllers during low power state
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* @phy_irq: IRQ number assigned for PHY to notify events like id and line
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state changes.
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* @pclk: clock struct of iface_clk.
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* @core_clk: clock struct of core_bus_clk.
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* @sleep_clk: clock struct of sleep_clk for USB PHY.
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* @phy_reset_clk: clock struct of phy_reset_clk for USB PHY. This clock is
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a reset only clock and resets the PHY, ULPI bridge and
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CSR wrapper.
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* @phy_por_clk: clock struct of phy_por_clk for USB PHY. This clock is
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a reset only clock and resets only the PHY (POR).
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* @phy_csr_clk: clock struct of phy_csr_clk for USB PHY. This clock is
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required to access PHY CSR registers via AHB2PHY interface.
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* @bus_clks: bimc/snoc/pcnoc clock struct.
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* @core_reset: Reset control for core_clk
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* @phy_reset: Reset control for phy_reset_clk
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* @phy_por_reset: Reset control for phy_por_clk
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* @default_noc_mode: default frequency for NOC clocks - SVS or NOM
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* @core_clk_rate: core clk max frequency
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* @regs: ioremapped register base address.
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* @usb_phy_ctrl_reg: relevant PHY_CTRL_REG register base address.
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* @inputs: OTG state machine inputs(Id, SessValid etc).
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* @sm_work: OTG state machine work.
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* @sm_work_pending: OTG state machine work is pending, queued post pm_resume
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* @resume_pending: USB h/w lpm_exit pending. Done on next sm_work run
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* @pm_suspended: OTG device is system(PM) suspended.
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* @pm_notify: Notifier to receive system wide PM transition events.
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It is used to defer wakeup events processing until
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system is RESUMED.
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* @in_lpm: indicates low power mode (LPM) state.
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* @async_int: IRQ line on which ASYNC interrupt arrived in LPM.
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* @cur_power: The amount of mA available from downstream port.
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* @otg_wq: Strict order otg workqueue for OTG works (SM/ID/SUSPEND).
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* @chg_work: Charger detection work.
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* @chg_state: The state of charger detection process.
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* @chg_type: The type of charger attached.
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* @chg_detection: True if PHY is doing charger type detection.
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* @bus_perf_client: Bus performance client handle to request BUS bandwidth
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* @host_bus_suspend: indicates host bus suspend or not.
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* @device_bus_suspend: indicates device bus suspend or not.
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* @bus_clks_enabled: indicates pcnoc/snoc/bimc clocks are on or not.
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* @is_ext_chg_dcp: To indicate whether charger detected by external entity
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SMB hardware is DCP charger or not.
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* @ext_id_irq: IRQ for ID interrupt.
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* @phy_irq_pending: Gets set when PHY IRQ arrives in LPM.
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* @id_state: Indicates USBID line status.
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* @rm_pulldown: Indicates pulldown status on D+ and D- data lines.
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* @dpdm_desc: Regulator descriptor for D+ and D- voting.
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* @dpdm_rdev: Regulator class device for dpdm regulator.
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* @dbg_idx: Dynamic debug buffer Index.
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* @dbg_lock: Dynamic debug buffer Lock.
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* @buf: Dynamic Debug Buffer.
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* @max_nominal_system_clk_rate: max freq at which system clock can run in
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nominal mode.
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* @sdp_check: SDP detection work in case of USB_FLOAT power supply
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* @notify_charger_work: Charger notification work.
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* @enable_sdp_check_timer: Timer for SDP charger to check enumeration.
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*/
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struct msm_otg {
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struct usb_phy phy;
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struct msm_otg_platform_data *pdata;
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struct platform_device *pdev;
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int irq;
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int async_irq;
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int phy_irq;
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struct clk *xo_clk;
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struct clk *pclk;
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struct clk *core_clk;
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struct clk *sleep_clk;
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struct clk *phy_reset_clk;
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struct clk *phy_por_clk;
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struct clk *phy_csr_clk;
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struct clk *bus_clks[USB_NUM_BUS_CLOCKS];
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struct clk *phy_ref_clk;
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struct reset_control *core_reset;
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struct reset_control *phy_reset;
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struct reset_control *phy_por_reset;
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long core_clk_rate;
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long core_clk_svs_rate;
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long core_clk_nominal_rate;
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enum usb_noc_mode default_noc_mode;
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struct resource *io_res;
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void __iomem *regs;
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void __iomem *phy_csr_regs;
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void __iomem *usb_phy_ctrl_reg;
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#define ID 0
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#define B_SESS_VLD 1
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#define A_BUS_SUSPEND 14
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unsigned long inputs;
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struct work_struct sm_work;
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bool sm_work_pending;
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bool resume_pending;
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atomic_t pm_suspended;
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struct notifier_block pm_notify;
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atomic_t in_lpm;
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bool err_event_seen;
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int async_int;
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unsigned int cur_power;
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struct workqueue_struct *otg_wq;
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struct delayed_work chg_work;
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struct delayed_work id_status_work;
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enum usb_chg_state chg_state;
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enum usb_chg_type chg_type;
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bool chg_detection;
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unsigned int dcd_time;
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unsigned long caps;
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uint32_t bus_perf_client;
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bool host_bus_suspend;
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bool device_bus_suspend;
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bool bus_clks_enabled;
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/*
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* Allowing PHY power collpase turns off the HSUSB 3.3v and 1.8v
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* analog regulators while going to low power mode.
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* Currently only 28nm PHY has the support to allowing PHY
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* power collapse since it doesn't have leakage currents while
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* turning off the power rails.
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*/
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#define ALLOW_PHY_POWER_COLLAPSE BIT(0)
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/*
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* Allow PHY RETENTION mode before turning off the digital
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* voltage regulator(VDDCX).
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*/
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#define ALLOW_PHY_RETENTION BIT(1)
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/*
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* Allow putting the core in Low Power mode, when
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* USB bus is suspended but cable is connected.
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*/
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#define ALLOW_LPM_ON_DEV_SUSPEND BIT(2)
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/*
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* Allowing PHY regulators LPM puts the HSUSB 3.3v and 1.8v
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* analog regulators into LPM while going to USB low power mode.
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*/
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#define ALLOW_PHY_REGULATORS_LPM BIT(3)
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/*
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* Allow PHY RETENTION mode before turning off the digital
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* voltage regulator(VDDCX) during host mode.
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*/
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#define ALLOW_HOST_PHY_RETENTION BIT(4)
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/*
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* Allow VDD minimization without putting PHY into retention
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* for fixing PHY current leakage issue when LDOs ar turned off.
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*/
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#define ALLOW_VDD_MIN_WITH_RETENTION_DISABLED BIT(5)
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/*
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* PHY can keep D+ pull-up during peripheral bus suspend and
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* D+/D- pull-down during host bus suspend without any
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* re-work. This is possible only when PHY DVDD is supplied
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* by a PMIC LDO (unlike VDDCX/VDDMX).
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*/
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#define ALLOW_BUS_SUSPEND_WITHOUT_REWORK BIT(6)
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unsigned long lpm_flags;
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#define PHY_PWR_COLLAPSED BIT(0)
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#define PHY_RETENTIONED BIT(1)
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#define XO_SHUTDOWN BIT(2)
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#define CLOCKS_DOWN BIT(3)
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#define PHY_REGULATORS_LPM BIT(4)
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int reset_counter;
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unsigned int online;
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dev_t ext_chg_dev;
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struct pinctrl *phy_pinctrl;
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bool is_ext_chg_dcp;
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struct qpnp_vadc_chip *vadc_dev;
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int ext_id_irq;
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bool phy_irq_pending;
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enum usb_id_state id_state;
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bool rm_pulldown;
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struct regulator_desc dpdm_rdesc;
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struct regulator_dev *dpdm_rdev;
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/* Maximum debug message length */
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#define DEBUG_MSG_LEN 128UL
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/* Maximum number of messages */
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#define DEBUG_MAX_MSG 256UL
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unsigned int dbg_idx;
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rwlock_t dbg_lock;
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char (buf[DEBUG_MAX_MSG])[DEBUG_MSG_LEN]; /* buffer */
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unsigned int vbus_state;
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unsigned int usb_irq_count;
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int pm_qos_latency;
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unsigned int notify_current_mA;
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struct pm_qos_request pm_qos_req_dma;
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struct delayed_work perf_vote_work;
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struct delayed_work sdp_check;
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struct work_struct notify_charger_work;
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bool enable_sdp_check_timer;
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};
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struct ci13xxx_platform_data {
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u8 usb_core_id;
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int *tlmm_init_seq;
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int tlmm_seq_count;
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/*
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* value of 2^(log2_itc-1) will be used as the interrupt threshold
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* (ITC), when log2_itc is between 1 to 7.
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*/
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int log2_itc;
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bool l1_supported;
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bool enable_ahb2ahb_bypass;
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bool enable_streaming;
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bool enable_axi_prefetch;
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};
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#ifdef CONFIG_USB_BAM
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void msm_bam_set_usb_host_dev(struct device *dev);
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int msm_do_bam_disable_enable(enum usb_ctrl ctrl);
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#else
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static inline void msm_bam_set_usb_host_dev(struct device *dev) {}
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static inline int msm_do_bam_disable_enable(enum usb_ctrl ctrl)
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{ return true; }
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#endif
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#ifdef CONFIG_USB_CI13XXX_MSM
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void msm_hw_soft_reset(void);
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#else
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static inline void msm_hw_soft_reset(void)
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{
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}
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#endif
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#endif
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170
include/linux/usb/msm_hsusb_hw.h
Normal file
170
include/linux/usb/msm_hsusb_hw.h
Normal file
@ -0,0 +1,170 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__
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#define __LINUX_USB_GADGET_MSM72K_UDC_H__
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/* USB phy selector - in TCSR address range */
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#define USB2_PHY_SEL 0xfd4ab000
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#define USB_AHBBURST (MSM_USB_BASE + 0x0090)
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#define USB_AHBMODE (MSM_USB_BASE + 0x0098)
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#define USB_GENCONFIG (MSM_USB_BASE + 0x009C)
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#define USB_GENCONFIG_2 (MSM_USB_BASE + 0x00a0)
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#define USB_HS_GPTIMER_BASE (MSM_USB_BASE + 0x80)
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#define ULPI_TX_PKT_EN_CLR_FIX BIT(19)
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#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
|
||||
#define USB_HS_APF_CTRL (MSM_USB_BASE + 0x0380)
|
||||
|
||||
#define APF_CTRL_EN BIT(0)
|
||||
|
||||
#define USB_USBCMD (MSM_USB_BASE + 0x0140)
|
||||
#define USB_USBSTS (MSM_USB_BASE + 0x0144)
|
||||
#define USB_PORTSC (MSM_USB_BASE + 0x0184)
|
||||
#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
|
||||
#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
|
||||
#define USB_PHY_CTRL (MSM_USB_BASE + 0x0240)
|
||||
#define USB_PHY_CTRL2 (MSM_USB_BASE + 0x0278)
|
||||
|
||||
#define GENCONFIG_2_SESS_VLD_CTRL_EN BIT(7)
|
||||
#define GENCONFIG_2_LINESTATE_DIFF_WAKEUP_EN BIT(12)
|
||||
#define GENCONFIG_2_SYS_CLK_HOST_DEV_GATE_EN BIT(13)
|
||||
#define GENCONFIG_2_DPSE_DMSE_HV_INTR_EN BIT(15)
|
||||
#define USBCMD_SESS_VLD_CTRL BIT(25)
|
||||
|
||||
#define USBCMD_RESET 2
|
||||
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
|
||||
#define USB_FRINDEX (MSM_USB_BASE + 0x014C)
|
||||
|
||||
#define AHB2AHB_BYPASS BIT(31)
|
||||
#define AHB2AHB_BYPASS_BIT_MASK BIT(31)
|
||||
#define AHB2AHB_BYPASS_CLEAR (0 << 31)
|
||||
#define USB_L1_EP_CTRL (MSM_USB_BASE + 0x0250)
|
||||
#define USB_L1_CONFIG (MSM_USB_BASE + 0x0254)
|
||||
|
||||
#define L1_CONFIG_LPM_EN BIT(4)
|
||||
#define L1_CONFIG_REMOTE_WAKEUP BIT(5)
|
||||
#define L1_CONFIG_GATE_SYS_CLK BIT(7)
|
||||
#define L1_CONFIG_PHY_LPM BIT(10)
|
||||
#define L1_CONFIG_PLL BIT(11)
|
||||
|
||||
#define PORTSC_PHCD (1 << 23) /* phy suspend mode */
|
||||
#define PORTSC_PTS_MASK (3 << 30)
|
||||
#define PORTSC_PTS_ULPI (2 << 30)
|
||||
#define PORTSC_PTS_SERIAL (3 << 30)
|
||||
#define PORTSC_LS (3 << 10)
|
||||
#define PORTSC_LS_DM (1 << 10)
|
||||
#define PORTSC_CCS (1 << 0)
|
||||
|
||||
#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170)
|
||||
#define ULPI_RUN (1 << 30)
|
||||
#define ULPI_WRITE (1 << 29)
|
||||
#define ULPI_READ (0 << 29)
|
||||
#define ULPI_SYNC_STATE (1 << 27)
|
||||
#define ULPI_ADDR(n) (((n) & 255) << 16)
|
||||
#define ULPI_DATA(n) ((n) & 255)
|
||||
#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
|
||||
|
||||
#define GENCONFIG_BAM_DISABLE (1 << 13)
|
||||
#define GENCONFIG_TXFIFO_IDLE_FORCE_DISABLE (1 << 4)
|
||||
#define GENCONFIG_ULPI_SERIAL_EN (1 << 5)
|
||||
|
||||
/* synopsys 28nm phy registers */
|
||||
#define ULPI_PWR_CLK_MNG_REG 0x88
|
||||
#define OTG_COMP_DISABLE BIT(0)
|
||||
|
||||
#define ULPI_MISC_A 0x96
|
||||
#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1)
|
||||
#define ULPI_MISC_A_VBUSVLDEXT BIT(0)
|
||||
|
||||
#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */
|
||||
#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */
|
||||
#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */
|
||||
#define PHY_IDHV_INTEN (1 << 8) /* PHY ID HV interrupt */
|
||||
#define PHY_OTGSESSVLDHV_INTEN (1 << 9) /* PHY Session Valid HV int. */
|
||||
#define PHY_CLAMP_DPDMSE_EN (1 << 21) /* PHY mpm DP DM clamp enable */
|
||||
#define PHY_POR_BIT_MASK BIT(0)
|
||||
#define PHY_POR_ASSERT (1 << 0) /* USB2 28nm PHY POR ASSERT */
|
||||
#define PHY_POR_DEASSERT (0 << 0) /* USB2 28nm PHY POR DEASSERT */
|
||||
|
||||
/* OTG definitions */
|
||||
#define OTGSC_INTSTS_MASK (0x7f << 16)
|
||||
#define OTGSC_IDPU (1 << 5)
|
||||
#define OTGSC_ID (1 << 8)
|
||||
#define OTGSC_BSV (1 << 11)
|
||||
#define OTGSC_IDIS (1 << 16)
|
||||
#define OTGSC_BSVIS (1 << 19)
|
||||
#define OTGSC_IDIE (1 << 24)
|
||||
#define OTGSC_BSVIE (1 << 27)
|
||||
|
||||
/* USB PHY CSR registers and bit definitions */
|
||||
|
||||
#define USB_PHY_CSR_PHY_UTMI_CTRL0 (MSM_USB_PHY_CSR_BASE + 0x060)
|
||||
#define TERM_SEL BIT(6)
|
||||
#define SLEEP_M BIT(1)
|
||||
#define PORT_SELECT BIT(2)
|
||||
#define OP_MODE_MASK 0x30
|
||||
|
||||
#define USB_PHY_CSR_PHY_UTMI_CTRL1 (MSM_USB_PHY_CSR_BASE + 0x064)
|
||||
#define DM_PULLDOWN BIT(3)
|
||||
#define DP_PULLDOWN BIT(2)
|
||||
#define XCVR_SEL_MASK 0x3
|
||||
|
||||
#define USB_PHY_CSR_PHY_UTMI_CTRL2 (MSM_USB_PHY_CSR_BASE + 0x068)
|
||||
|
||||
#define USB_PHY_CSR_PHY_UTMI_CTRL3 (MSM_USB_PHY_CSR_BASE + 0x06c)
|
||||
|
||||
#define USB_PHY_CSR_PHY_UTMI_CTRL4 (MSM_USB_PHY_CSR_BASE + 0x070)
|
||||
#define TX_VALID BIT(0)
|
||||
|
||||
#define USB_PHY_CSR_PHY_CTRL_COMMON0 (MSM_USB_PHY_CSR_BASE + 0x078)
|
||||
#define SIDDQ BIT(2)
|
||||
|
||||
#define USB_PHY_CSR_PHY_CTRL1 (MSM_USB_PHY_CSR_BASE + 0x08C)
|
||||
#define ID_HV_CLAMP_EN_N BIT(1)
|
||||
|
||||
#define USB_PHY_CSR_PHY_CTRL2 (MSM_USB_PHY_CSR_BASE + 0x090)
|
||||
#define USB2_SUSPEND_N BIT(6)
|
||||
|
||||
#define USB_PHY_CSR_PHY_CTRL3 (MSM_USB_PHY_CSR_BASE + 0x094)
|
||||
#define CLAMP_MPM_DPSE_DMSE_EN_N BIT(2)
|
||||
|
||||
#define USB_PHY_CSR_PHY_CFG0 (MSM_USB_PHY_CSR_BASE + 0x0c4)
|
||||
|
||||
#define USB2_PHY_USB_PHY_IRQ_CMD (MSM_USB_PHY_CSR_BASE + 0x0D0)
|
||||
#define USB2_PHY_USB_PHY_INTERRUPT_SRC_STATUS (MSM_USB_PHY_CSR_BASE + 0x05C)
|
||||
|
||||
#define USB2_PHY_USB_PHY_INTERRUPT_CLEAR0 (MSM_USB_PHY_CSR_BASE + 0x0DC)
|
||||
#define USB2_PHY_USB_PHY_DPDM_CLEAR_MASK 0x1E
|
||||
|
||||
#define USB2_PHY_USB_PHY_INTERRUPT_CLEAR1 (MSM_USB_PHY_CSR_BASE + 0x0E0)
|
||||
|
||||
#define USB2_PHY_USB_PHY_INTERRUPT_MASK0 (MSM_USB_PHY_CSR_BASE + 0x0D4)
|
||||
#define USB2_PHY_USB_PHY_DP_1_0_MASK BIT(4)
|
||||
#define USB2_PHY_USB_PHY_DP_0_1_MASK BIT(3)
|
||||
#define USB2_PHY_USB_PHY_DM_1_0_MASK BIT(2)
|
||||
#define USB2_PHY_USB_PHY_DM_0_1_MASK BIT(1)
|
||||
|
||||
#define USB2_PHY_USB_PHY_INTERRUPT_MASK1 (MSM_USB_PHY_CSR_BASE + 0x0D8)
|
||||
|
||||
#define USB_PHY_IDDIG_1_0 BIT(7)
|
||||
|
||||
#define USB_PHY_IDDIG_RISE_MASK BIT(0)
|
||||
#define USB_PHY_IDDIG_FALL_MASK BIT(1)
|
||||
#define USB_PHY_ID_MASK (USB_PHY_IDDIG_RISE_MASK | USB_PHY_IDDIG_FALL_MASK)
|
||||
|
||||
#endif /* __LINUX_USB_GADGET_MSM72K_UDC_H__ */
|
||||
@ -177,6 +177,11 @@ struct usb_phy {
|
||||
/* reset the PHY clocks */
|
||||
int (*reset)(struct usb_phy *x);
|
||||
int (*drive_dp_pulse)(struct usb_phy *x, unsigned int pulse_width);
|
||||
|
||||
/* for notification of usb_phy_dbg_events */
|
||||
void (*dbg_event)(struct usb_phy *x,
|
||||
char *event, int msg1, int msg2);
|
||||
|
||||
};
|
||||
|
||||
/* for board-specific init logic */
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2011-2017, 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2011-2017, 2020-2021, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _USB_BAM_H_
|
||||
@ -409,6 +409,12 @@ static inline int get_qdss_bam_info(enum usb_ctrl cur_bam, u8 idx,
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool msm_usb_bam_enable(enum usb_ctrl ctrl, bool bam_enable)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* CONFIG_PM */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user