74 lines
2.0 KiB
ArmAsm
74 lines
2.0 KiB
ArmAsm
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/* mb.S: Out of line memory barriers.
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*
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* Copyright (C) 2005 David S. Miller (davem@davemloft.net)
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*/
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/* These are here in an effort to more fully work around
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* Spitfire Errata #51. Essentially, if a memory barrier
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* occurs soon after a mispredicted branch, the chip can stop
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* executing instructions until a trap occurs. Therefore, if
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* interrupts are disabled, the chip can hang forever.
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*
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* It used to be believed that the memory barrier had to be
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* right in the delay slot, but a case has been traced
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* recently wherein the memory barrier was one instruction
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* after the branch delay slot and the chip still hung. The
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* offending sequence was the following in sym_wakeup_done()
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* of the sym53c8xx_2 driver:
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*
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* call sym_ccb_from_dsa, 0
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* movge %icc, 0, %l0
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* brz,pn %o0, .LL1303
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* mov %o0, %l2
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* membar #LoadLoad
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*
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* The branch has to be mispredicted for the bug to occur.
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* Therefore, we put the memory barrier explicitly into a
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* "branch always, predicted taken" delay slot to avoid the
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* problem case.
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*/
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.text
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99: retl
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nop
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.globl mb
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mb: ba,pt %xcc, 99b
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membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad
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.size mb, .-mb
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.globl rmb
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rmb: ba,pt %xcc, 99b
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membar #LoadLoad
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.size rmb, .-rmb
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.globl wmb
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wmb: ba,pt %xcc, 99b
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membar #StoreStore
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.size wmb, .-wmb
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.globl membar_storeload
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membar_storeload:
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ba,pt %xcc, 99b
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membar #StoreLoad
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.size membar_storeload, .-membar_storeload
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.globl membar_storeload_storestore
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membar_storeload_storestore:
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ba,pt %xcc, 99b
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membar #StoreLoad | #StoreStore
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.size membar_storeload_storestore, .-membar_storeload_storestore
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.globl membar_storeload_loadload
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membar_storeload_loadload:
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ba,pt %xcc, 99b
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membar #StoreLoad | #LoadLoad
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.size membar_storeload_loadload, .-membar_storeload_loadload
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.globl membar_storestore_loadstore
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membar_storestore_loadstore:
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ba,pt %xcc, 99b
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membar #StoreStore | #LoadStore
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.size membar_storestore_loadstore, .-membar_storestore_loadstore
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